To allow use of TIFS RM services from SPL, a change has been made to
pass the RM boardcfg directly to TIFS from SPL before storing the RM
boardcfg in memory for DM to consume once it boots. However, on HS
silicon, the TIFS RM boardcfg processing modifies the passed blob in
place, which is passed as signing cert + RM blon, and is left as just
the raw RM blob. This then gets copied to the DM boardcfg shared
memory, and DM fails.
DM expects to have the signing cert + blob shared with it, so to allow
this to happen, copy the signing cert + RM blob first, and move sending
to TIFS after. The boardcfg gets modified in its original location but
we have already copied the cert and blob and they are passed to DM
unmodified.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
When booting with HS silicon, the system firmware image is 278270, which
is slightly larger than currently allocated amount.
This can cause unexpected behavior if this overlap interferes with other
things in memory, so increase this with a slightly margin added as well
to avoid any boot issues that can appear after system firmware gets
loaded.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).
Disable second port as its by default set to ICSS usage on EVM.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Parse MAC addresses from EEPROM and set them in the env. This is needed
to get MAC address for additional ethernet ports on the EVM.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed
ring mode, all other K3 SoCs have also been moved to this common
baseline. Therefore drop other modes such as
K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint.
There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Currently driver may end up caching disabled port ID as active
interface. Fix this by bailing out earlier in case port is marked
disabled in the DT.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
AM64 dual mode rings are modeled as pair of Rings objects which has common
configuration and memory buffer, but separate real-time control register
sets for each direction mem2dev (forward) and dev2mem (reverse).
AM64 rings must be requested only using k3_ringacc_request_rings_pair(),
and forward ring must always be initialized/configured. After this any
other Ringacc APIs can be used without any callers changes.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support
AM64x BCDMA Block copy channels.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
enable configs to save env in eMMC and FAT write.
Kconfig symbols for SYS_MMC_ENV_DEV and SYS_MMC_ENV_PART have been added by
commit 7d08077334. Therefore, move the
definitions of configs to corresponding board defconfig files and enable
configs to save env in eMMC.
Also enable config for FAT write in U-Boot.
Fixes: b5a074f43c ("board: ti: am64x: Add board support for am64x evm")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Function spl_boot_mode() is called in common/spl/spl_mmc.c, to find the
boot mode for a given boot device. This function was renamed to
spl_mmc_boot_mode() by commit e97590654a.
Therefore, rename spl_boot_mode to spl_mmc_boot_mode.
Fixes: 00b21f25aa ("arm: mach-k3: am642: Add support for boot device detection")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Update the default BOOTCOMMAND to provide an automatic and easier way
to configure ethernet PHY before loading the firmware.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII
operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN
controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1"
on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22),
PIN: 18.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Add config for torrent serdes and common clock framework.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra
phy driver. All of them are required for USB3 support
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add default lane function for torrent serdes.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Partially sync with Linux's dts to add the entries required for USB3
support on USB0.
Note that the default mode is still "peripheral" not "host". USB3 is
supported only for the host mode.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add support for probing and configuring Torrent serdes on J7200.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Upstream device tree got updated to use clock name as "ref" instead of
"usb2_refclk". Fix cdns3-ti.c to use the correct name.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.
This is an adaptation of the linux driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add a Sierra PHY driver with PCIe and USB support.
This driver is a port from the mainline linux driver.
The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.
There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself. Additionally there are
resets for each PHY lane.
The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.
The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required) for each lane
group, and then enable the PHY. Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY
One difference with the linux driver is that the PHY is
always reset after it is powered-on. This is because role
switching is not supported in u-boot and the cable
orientation is handled by the PHY reset.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add definitions for additional phy types that's used specifically for
Torrent SERDES.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The reset framework provides devm_reset_control_get_optional()
which can return NULL (not an error case). So all the other reset_ops
should handle NULL gracefully. Prepare the way for a managed reset
API by handling NULL pointers without crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
commit 6239cc8c4e upstream.
Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot.
MCU R5F nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid regressions, r5f nodes are kept intact.
These will be added in kernel in future.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
commit 70e167495a upstream.
Sync all J721e related v5.11-rc6 Linux kernel dts into U-Boot.
HBMC nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid any regressions, hbmc nodes are kept
intact. These will be added in kernel in future.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This reverts commit 25d50fd4c2. This will
prevent compilation from breaking after Linux v5.11-rc6 dts is synced into
U-Boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Many files in this driver were mistakenly added with execute permission
set, so correct mode to 664 for all files to match others in u-boot
source tree.
Reported-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Ensure that drivers/ram/k3-ddrss is part of the include path search list
so that headers can be included by all files that are part of the
driver, including those under 16bit/ and 32bit/ paths.
Reported-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
In HyperFlash boot mode it is required to detect the state of onboard DIP
switch and based on its state, set the status in corresponding DT nodes.
Add support for this by enabling configs of GPIO driver model and FDT
library for parsing in SPL.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
In the boot flow of HyperFlash boot mode, initially the clock rate is set
by ROM and the same is used by R5 and A72 SPLs. By default the status of
HyperFlash DT node is disabled, which implies that w.r.t R5 SPL HyperFlash
is disabled and the clocks assigned to it can now be reassigned. In
common/spl/spl_nor.c the images are directly loaded into RAM without
setting the clock. In case of R5 SPL, tispl.bin image is first loaded and
then other devices are probed because of which the clock rate set by ROM
for HyperFlash does not change and image loaded is correct. However, by the
time the A72 SPL starts executing, the clock rate assigned to HyperFlash
gets changed. So, if the clock rate is not set again, the reads from
HyperFlash will be corrupted leading to a broken boot.
Fix this by probing the hbmc-am654 driver using
uclass_get_device_by_driver() which sets the default clock rate before
calling the driver probe, when the state of SW3.1 dip switch on the board
is set to 1. Also, define the function spl_perform_fixups() in case of R5
SPL too, so that status of HyperFlash in tispl.bin image can be set
appropriately for device probe.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
On J721e R5 SPL, dfu buffer for loading sysfw.itb image gets allocated
before DRAM gets initialized. So, the buffer gets allocated in MCU L3 RAM.
The current buffer size to be allocated is 256KB and the available total
heap memory is 0x70000 (448KB). This leads to NOMEM errors during
allocation.
In other cases when constraints such as above are not present fix the size
of buffers to the sector size in OSPI for proper functioning.
Also, if CONFIG_SYS_DFU_DATA_BUF_SIZE is defined and
CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then the max
file size for dfu transfer is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE.
Fix these by setting appropriate buffer sizes in their respective
defconfig files and defining the max file size as 8 MB which is the default
dfu buffer size.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Currently the config options CONFIG_SYS_DFU_DATA_BUF_SIZE and
CONFIG_SYS_DFU_MAX_FILE_SIZE are being set in include/configs/<board>.h
files and also in <board_name>_defconfig files without a Kconfig option. It
is easier for users to set these configs in defconfig files than in config
header files as they are a part of the source code.
Add Kconfig symbols, and update the defconfigs by using tools/moveconfig.py
script.
Suggested-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
AM642 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM642 SoC. It supports the following interfaces:
* 2 GB LPDDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode
* x1 USB 3.0 Type-A port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x2 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin Raspberry Pi compatible GPIO header
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 54-pin header for Programmable Realtime Unit (PRU) IO pins
* Interface for remote automation. Includes:
* power measurement and reset control
* boot mode change
Add basic support for AM642 SK.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Dave Gerlach
Vignesh Raghavendra
Aswath Govindraju
Kishon Vijay Abraham I
Faiz Abbas
Jean-Jacques Hiblot
Alan Douglas
Lokesh Vutla