LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
50,111 Commits 68 Branches 337 Tags 212 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
Bai Ping cb43368096 MLK-20163-02 imx8m: ddr: update the dram driver for i.MX8M 
Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
 2018-11-02 20:50:11 -05:00
Bai Ping 65fed31a52 MLK-19777-03: imx8mm_evk: Optimize the ddr4 init flow 
Optimize the DDR4 init flow. Split the common flow
with the DDR specific timing config. So the common
flow can be reused.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
 2018-10-01 17:25:25 +08:00
Bai Ping fea0b43ca7 MLK-18431-02: add a more generic dram init flow for imx8m 
the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.

the same method can be use for DDR4. will be added later.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
 2018-08-05 22:36:07 -07:00