Although this is not strictly needed as the tiboot3.bin file on J721e
does not contain SYSFW like other platforms, renaming this way matches
the others and helps simplify integration layers.
Signed-off-by: Andrew Davis <afd@ti.com>
Although this is not strictly needed as the tiboot3.bin file on AM65x
does not contain SYSFW like other platforms, renaming this way matches
the others and helps simplify integration layers.
A symlink is added to keep the default for AM65x as GP.
Signed-off-by: Andrew Davis <afd@ti.com>
The name of the tiboot3.bin should match the SYSFW contents. This makes
it easy to figure out what SYSFW was used for each and matches how
k3-image-gen used to name these files.
Signed-off-by: Andrew Davis <afd@ti.com>
The AM62x LP SK board has separate set of device tree. Update
Makefile with k3-am62-r5-lp-sk.dts and k3-am62-lp-sk.dts device
tree to add support of AM62x LP SK.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
The AM62x LP SK board is similar to AM62x SK board, but
has a own set of attributes that requires different device
tree on each stage of bootloader. These dt changes add
support for AM62x LP SK at R5 SPL.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
To prepare for upcoming derivative boards based on the
AM625 SK, sync the dts and dtsi files for this board so
that the derivative boards will inherit and retain only
those parts that are different in the current dts file.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
The AM62x LP SK board is similar to the AM62x SK board,
but has some significant changes that requires different
device tree.
The differences are mainly:
- AM62x SoC in the AMC package that meets AECQ100 automotive standard.
- LPDDR4 versus DDR4 on the AM62x SK.
- TPS65219 PMIC instead of discrete regulators.
- IO expander pin names are wired differently.
- Second ethernet port is currently disabled as the boards do not have
the part physically installed.
- OSPI NAND vs OSPI NOR.
- No WLAN chip instead a SDIO M.2 connector.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Move to using binman to generate tispl.bin which is used to generate the
final flash.bin bootloader for iot2050 boards.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Support added for HS and GP boot binaries for AM62ax.
tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned and u-boot.img_unsigned: For GP
devices
It is to be noted that the bootflow followed by AM62ax requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Support added for HS and GP boot binaries for AM62
tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned, u-boot.img_unsigned: For GP
devices
It is to be noted that the bootflow followed by AM62 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Support added for HS and GP boot binaries for J721S2.
tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned, u-boot.img_unsigned: For GP
devices
It is to be noted that the bootflow followed by J721S2 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Support added for HS and GP boot binaries for AM64x.
tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned, u-boot.img_unsigned: For GP
devices
Note that the bootflow followed by AM64x requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* sysfw
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* ATF
* OPTEE
* A53 SPL
* A53 SPL dtbs
u-boot.img:
* A53 U-Boot
* A53 U-Boot dtbs
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Support added for HS and GP boot binaries for J7200.
tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned and u-boot.img_unsigned: For GP
devices
It is to be noted that the bootflow followed by J7200 requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
By providing entries in the binman node of the device tree, binman will
be able to find and package board config artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
It will also pick out the R5 SPL and sign it with the help of TI signing
entry and generate the final tiboot3.bin.
Entries for A72 build have been added to k3-j721e-binman.dtsi to
generate tispl.bin and u-boot.img.
Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images
In HS-SE, the encrypted system firmware binary must be signed along with
the signed certificate binary.
tiboot3.bin and sysfw-j721e_sr1_1-hs.itb: For HS-SE devices
tiboot3.bin_fs and sysfw-j721e_sr2-hs-fs.itb: For HS-FS devices
tiboot3.bin_unsigned and sysfw-j721e-gp-evm.itb: For GP devices
<filename>.bin/img: For HS devices
<filename>.bin_unsigned/img_unsigned: For GP devices
Intention of patch is to move signing and packaging to binman,
thus making makefile target only if binman is not enabled.
It is to be noted that the bootflow followed by J721E requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
sysfw.itb:
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Board config binary artifacts must be generated to be used by binman to
package sysfw.itb and tiboot3.bin for all K3 devices.
For devices that follow combined flow, these board configuration
binaries must again be packaged into a combined board configuration
blobs to be used by binman to package tiboot3.bin.
Add common k3-binman.dtsi to generate all the board configuration
binaries needed.
Also add custMpk.pem and ti-degenerate-key.pem needed for signing GP and
HS bootloader images common to all K3 devices.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Main domain ESM support is needed to configure main domain watchdog
interrupts to generate ESM pin events. On J7200 boards ESM error pin
output is propagated to PMIC to generate reset.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
MAIN domain ESM support was already added for J721E to configure main
domain watchdog interrupts to generate ESM pin events. Move the main_esm
node to be in sync with kernel dts. Also add register mapping for ESM in
J721E.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Since the MDIO driver is not DM enabled and the CPSW driver is
responsible for configuring the pins corresponding to MDIO as well,
add the MDIO pinctrl in the cpsw3g device-tree node as a HACK in
the k3-am642-sk-u-boot.dtsi file.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Add support for USB controllers and enable the USB to boot via DFU.
The USB node changes are in sync with linux kernel.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
commit 1e666512fb00d3aed6e32db2c22579e87d977d76 upstream
Update the DDR settings to those generated using 0.6 version of
Jacinto 7 DDRSS Register Configuration tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
commit b99d710fe090b1af7cadd4ab09dbf205169e3090 upstream
Update the DDR settings to those generated using 0.9.1 version of
Jacinto 7 DDRSS Register Configuration tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j721s2.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Enable CPSW3G MAC Port 1 at U-Boot stage.
Since the MDIO driver is not DM enabled, add the MDIO pinctrl in the
cpsw3g device-tree node as a HACK.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[ upstream commit 53f02be32e1fd387a37ef9a10a55cbeed425f599 ]
adds a53 cluster to control from the rproc driver
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[ upstream commit 9a36735b0f62efc892d3b0eb2c020487c72359f9 ]
adds a53 cluster to control from the rproc driver
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[ upstream commit 3922cf6295c772e703d8c1f1044f2ead22ef02c7 ]
adds a53 cluster to control from the rproc driver
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[ upstream commit 7fe7920c5e8316e112f66cf2213e3e9df6e35fc2 ]
adds a53 cluster to control from the rproc driver
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[ upstream commit dcdcbde2bbbc770573c0a8da19a937e0d8ee6d80 ]
adds a72 cluster to control from the rproc driver
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[ upstream commit bdbd6688534cd998edc7dc057b67a70c5a5eeccb ]
adds a72 cluster to control from the rproc driver
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[ upstream commit ab3df39ffa981043302bac6300a6cebbbf550a5b ]
adds a72 cluster to control from the rproc driver
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Enable MCU CPSW2G at U-Boot stage.
Since the MDIO driver is not DM enabled and the CPSW driver is
responsible for configuring the pins corresponding to MDIO as well,
add the MDIO pinctrl in the mcu_cpsw device-tree node as a HACK in
the k3-j784s4-evm-u-boot.dtsi file.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Add device tree nodes to enable MCU CPSW with J784S4 EVM.
Linux kernel device tree patch for the same is at:
https://git.kernel.org/ti/linux/c/6cd4b7cfbcca
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
TISCI device ID for main_navss and mcu_navss nodes are missing in
the device tree. Add them.
Linux kernel device tree fix for the same set of NAVSS nodes is at:
https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
Fixes: b4b077edc8 ("arm: dts: introduce j784s4 dtbs from linux kernel")
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
In order to reduce duplication, let k3-j784s4-r5-evm.dts inherit from
k3-j784s4-evm.dts and k3-j784s4-u-boot.dtsi.
This is based on the patch by Nishanth Menon <nm@ti.com> at:
https://lore.kernel.org/r/20230414075726.387461-13-nm@ti.com/
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
This reverts commit 5717294230. This
does not exist in upstream kernel.org and breaks boot on DRA7-EVMs.
Drop the same.
Signed-off-by: Andrew Davis <afd@ti.com>
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.
Signed-off-by: Andrew Davis <afd@ti.com>
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.
Signed-off-by: Andrew Davis <afd@ti.com>
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.
Signed-off-by: Andrew Davis <afd@ti.com>
Andrew Davis
Nitin Yadav
Neha Malcom Francis
Gowtham Tammana
Siddharth Vadapalli
Bryan Brattlof
Aswath Govindraju
Manorit Chawdhry
Jayesh Choudhary