Commit Graph

7 Commits

Author SHA1 Message Date
Bai Ping 566b798213 MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip
Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
2018-11-20 18:21:35 +08:00
Bai Ping cb43368096 MLK-20163-02 imx8m: ddr: update the dram driver for i.MX8M
Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-02 20:50:11 -05:00
Bai Ping dac64635e9 MLK-19907 imx8m: ddr4: Update the refresh_mode setting
Update the refresh_mode setting. Clear the RFSHCTL3.refresh_mode bit
to set it to normal_mode.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2018-10-12 16:28:56 +08:00
Bai Ping 65fed31a52 MLK-19777-03: imx8mm_evk: Optimize the ddr4 init flow
Optimize the DDR4 init flow. Split the common flow
with the DDR specific timing config. So the common
flow can be reused.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-01 17:25:25 +08:00
Bai Ping 258db72309 MLK-19777-01: imx8mm: rename the lpddr4_ddrphy_train file
For LPDDR4 or DDR4, the ddr phy train flow is the same.
So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'.
make it more common for reuse and move it to driver/ddr/imx8m/.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-01 17:25:24 +08:00
Luo Ji 9337077a29 MA-12219 [Android] Fix build errors for imx8mm
Android build use different tool chain(gcc 4.9) with yocto(gcc 6.2),
'for' loop initial declarations are not supported in C90, define the
variable first before use it.

Test: build pass for imx8mm_evk.

Change-Id: Idf9a9f21626a02e2e679d2e74410378cd143c3f1
Signed-off-by: Luo Ji <ji.luo@nxp.com>
2018-08-07 11:50:46 +08:00
Bai Ping fea0b43ca7 MLK-18431-02: add a more generic dram init flow for imx8m
the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.

the same method can be use for DDR4. will be added later.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
2018-08-05 22:36:07 -07:00