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3 Commits

Author SHA1 Message Date
Aswath Govindraju 4f260bbeeb dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC 
There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES
lane mux can select upto 4 different IPs. Define all the possible
functions.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
 2022-02-08 09:41:27 -05:00
Kishon Vijay Abraham I 2b0f7dee5f dt-bindings: ti-serdes-mux: Add defines for AM64 SoC 
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-7-kishon@ti.com
 2021-07-27 10:56:53 +05:30
Lokesh Vutla 70e167495a arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot 
Sync all J721e related v5.11-rc6 Linux kernel dts into U-Boot.
HBMC nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid any regressions, hbmc nodes are kept
intact. These will be added in kernel in future.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
 2021-02-04 20:37:57 +05:30