u-boot

Commit Graph

Author	SHA1	Message	Date
Marek Szyprowski	814e1a4b8c	rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>	2020-07-10 14:10:43 -04:00
Matthias Brugger	8e3361c88a	ARM: bcm283x: Move BCM283x_BASE to a global variable We move the per SOC define BCM283x_BASE to a global variable. This is a first step to provide a single binary for several bcm283x SoCs. Signed-off-by: Matthias Brugger <mbrugger@suse.com>	2019-11-24 10:46:27 +01:00

Author

SHA1

Message

Date

Marek Szyprowski

814e1a4b8c

rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

2020-07-10 14:10:43 -04:00

Matthias Brugger

8e3361c88a

ARM: bcm283x: Move BCM283x_BASE to a global variable

We move the per SOC define BCM283x_BASE to a global variable.
This is a first step to provide a single binary for several bcm283x
SoCs.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>

2019-11-24 10:46:27 +01:00

2 Commits