2 Commits

Author	SHA1	Message	Date
David Wu	2e4ce50d1a	rockchip: clk: Add rv1108 SARADC clock support ... The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-10-01 00:33:29 +02:00
Andy Yan	bae2f282a9	rockchip: clk: Add rv1108 clock driver ... Add clock driver support for Rockchip rv1108 soc Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>	2017-06-07 07:29:25 -06:00