While calculating the length of the property value to be replaced with,
also include the "\0" character. This makes the length of the new property
value "host" to be 5 and not 4.
Fixes: d0d92256cb ("arm: mach-k3: am642_init: Fix the length of new property value in fdt_find_and_setprop()")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
HS400 speed mode is now supported in J7200 SoC[1]. Therefore add
mmc-hs400-1_8v tag in sdhci0 device tree node.
Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf,
(SPRUIU1A – JULY 2020 – REVISED JANUARY 2021)
[2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf,
(SPRSP57B – APRIL 2020 – REVISED JANUARY 2021)
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Add voltage and thermal management (VTM) node. The efuse values for the
OPPs are stored under the VTM, and is needed for AVS class 0 support.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
The `struct udevice *` reference is needed for either of the
K3_LOAD_SYSFW, K3_AM64_DDRSS config guards. Adding the missing
K3_AM64_DDRSS guard.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Add ICSSG2 EMAC support. DT nodes are fetch from kernel 5.10
Add U-Boot specific properties are kept under
k3-am654-base-board-u-boot.dtsi
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
k3-am654-idk.dts is a dts file and should not be included in an overlay.
Fix it by including right overlay - k3-am654-sr1.dts.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The AM65x family of SoCs has two Silicon Revisions - SR1.0 and SR2.0.
The current dtsi and dts files all define the nodes to represent and/or
use the AM65x SR2.0. Add a new overlay file 'k3-am654-sr1.dts' to specify
the delta differences between the two Silicon revisions. This overlay
should be applied on top of the actual AM65x board dts files.
The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the
subsequent IP revision used on J721E SoCs. The ICSSG IP on AM65x SR2.0
SoCs have two new custom auxiliary PRU cores called Transmit PRUs
(Tx_PRUs) in addition to the existing PRUs and RTUs, but these are
not present on AM65x SR1.0 SoCs. The Tx_PRU nodes are added and enabled
by default in the base k3-am65-main.dtsi file, but these are absent on
SR1.0, so mark them disabled specifically.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
that are present on the K3 AM65x SoCs. The three ICSSGs are identical
to each other for the most part, with the ICSSG2 supporting slightly
enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
is represented by a PRUSS subsystem node. These nodes are enabled by
default.
DT nodes are fetch from Linux 5.10 Kernel.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
So far all the u-boot specific properties for both r5 and a53 are
placed in k3-am654-base-board-u-boot.dtsi. But there are few a53
nodes that should be updated but doesn't belong to r5. So create a
separate r5 specific u-boot dtsi.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
NB0 is bridge to SRAM and NB1 is bridge to DDR.
To ensure that SRAM transfers are not stalled due to
delays during DDR refreshes, SRAM traffic should be higher
priority (threadmap=2) than DDR traffic (threadmap=0).
This patch does just that.
This is required to fix ICSSG TX lock-ups due to delays in
MSMC transfers due to incorrect Northbridge configuration.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update the ddr settings to use the DDR reg config tool rev 0.6.0.
This enables 2666MTs DDR configuration.
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Update the ddr settings to use the DDR reg config tool rev 0.6.0.
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add ti,ddr-freq0 entry for the DDR controller used by j721e and j7200
and provide a value in the corresponding SoC specific configuration
files.
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
The J721E PM1 SoM board uses a TPS65917 PMIC. The MMC SDCard
IO supply is provided by the LDO1 regulator from this PMIC.
Add a separate PM1 SoM specific dts file with this PMIC, and
make the necessary adjustments for the regulator consumer usage
changes.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[s-anna@ti.com: port to 2021 LTS and split up the A72 dts]
Signed-off-by: Suman Anna <s-anna@ti.com>
The J721E PM1 SoM uses TPS65917 PMIC, and uses a different regulator
(SMPS12) as the supply for A72 AVS Class 0. Add support for this by
fixing up the DT supply dynamically based on the board version to
get the right phandle for avs supply regulator.
The same k3-j721e-r5-common-proc-board.dts file is used to avoid
dynamic detection for R5 SPL DTB, with the TPS65917 PMIC nodes
added. Both PMIC nodes are present (not at all ideal), but their
sole usage is to provide for AVS Class 0 functionality.
There is no plan to upstream this support, and hence the simpler
HACK approach is taken.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[s-anna@ti.com: port to 2021 LTS and split up the R5 portion]
Signed-off-by: Suman Anna <s-anna@ti.com>
Due to a limitation for USB DFU boot mode, SPL load address has to be less
than or equal to 0x70001000. So, load address of SPL and ATF have been
moved to 0x70000000 and 0x701a0000 respectively.
Also, the maximum size of ATF has been increased to 0x1c000 [1].
Therefore, update ATF's location and maximum size accordingly in the device
tree file.
[1] - https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=2fb5312f61a7de8b7a70e1639199c4f14a10b6f9
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
For USB DFU boot mode there is a limitation on the load address of boot
images that they have to be less than 0x70001000. Therefore, move the
SPL_TEXT_BASE address to 0x70000000.
Currently ATF is being loaded at 0x70000000, if the SPL is being loaded at
0x70000000 then ATF would overwrite SPL image when loaded. Therefore, move
the location of ATF to a latter location in SRAM, past the SPL image. Also
rearrange the EEPROM and BSS data on top of ATF.
Given below is the placement of various data sections in SRAM
┌──────────────────────────────────────┐0x70000000
│ │
│ │
│ │
│ SPL IMAGE (Max size 1.5 MB) │
│ │
│ │
│ │
├──────────────────────────────────────┤0x7017FFFF
│ │
│ SPL STACK │
│ │
├──────────────────────────────────────┤0x70192727
│ GLOBAL DATA(216 B) │
├──────────────────────────────────────┤0x701927FF
│ │
│ INITIAL HEAP (32 KB) │
│ │
├──────────────────────────────────────┤0x7019A7FF
│ │
│ BSS (20 KB) │
├──────────────────────────────────────┤0x7019F7FF
│ EEPROM DATA (2 KB) │
├──────────────────────────────────────┤0x7019FFFF
│ │
│ │
│ ATF (123 KB) │
│ │
│ │
├──────────────────────────────────────┤0x701BEBFB
│ BOOT PARAMETER INDEX TABLE (5124 B)│
├──────────────────────────────────────┤0x701BFFFF
│ │
│SYSFW FIREWALLED DUE TO A BUG (128 KB)│
│ │
├──────────────────────────────────────┤0x701DFFFF
│ │
│ DMSC CODE AREA (128 KB) │
│ │
└──────────────────────────────────────┘0x701FFFFF
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Add support for providing ATF load address with a Kconfig symbol.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
EMIF tool for J7200 is now updated to 0.5.0
* Includes LPDDR with 2666MTs configuration
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
AM64x SK lp4ddr 800MHz frequency configuration was initial data which
is still under investigation for random failures and is expected to be
tweaked. Lets delete this initial configuration for now till the final
values are stabilized.
Suggested-by: Lokesh Vutla <lokeshvutla@ti.com>
Suggested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
AM64x SK lp4ddr with 800MHz frequency config which was initial data
facing random failures. Alternatively, lp4ddr configuration with
667MHz frequency is functioning stable. Lets Add AM64x SK lp4ddr
configuration data for 667MHz frequency. Also, Update
k3-am642-r5-sk.dts file to use the 667MHz dtsi file.
Validated memtester test on 900MB of lp4 ddr memory with multiple
iterations.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: James Doublesin <doublesin@ti.com>
The default U-Boot environment variables and design are all set up for
both the MAIN R5FSS clusters to be in Split-mode. This is the setting
in v2021.01 U-Boot and the dt nodes are synched with the newer kernel
binding property names in commit c118d25546 ("remoteproc: k3_r5:
Sync to upstreamed kernel DT property names").
The modes for both the clusters got switched back to LockStep mode by
mistake in commit 16c0c84460 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6
dts into U-Boot"). This throws the following warning messages when
early-booting the cores using default env variables,
k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode
Load Remote Processor 3 with data@addr=0x82000000 98484 bytes: Failed!
k3_r5f_rproc r5f@5f00000: Invalid op: Trying to start secondary core 9 in lockstep mode
Load Remote Processor 5 with data@addr=0x82000000 98484 bytes: Failed!
Fix this by switching back both the clusters to the expected Split-mode.
Make this mode change in the u-boot specific dtsi file to avoid such
sync overrides in the future until the kernel dts is also switched to
Split-mode by default.
Fixes: 16c0c84460 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot")
Reported-by: Minas Hambardzumyan <minas@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
While Kernel expects ethernetX alias to point to individual ethernet
ports in case of multi MAC ethernet controller, U-Boot DM core expects
ethernetX alias to point to the node that ethernet (am65-cpsw-nuss)
driver binds to. Hence aliases copied from kernel DT will
leads to 3 issues:
- ethernet interfaces on K3 SoCs get a different seq number than that of
intended alias (eg.: CPSW port0 on AM65x get eth1 instead of eth0).
- "ethaddr" env variable is no longer set to eFuse MAC address.
- U-Boot FDT fixup code won't update MAC address in Kernel's DT
due to missing "ethaddr" variable.
Fix this by updating alias to point to CPSW node in -u-boot.dtsi file
for all K3 SoCs to match U-Boot's expectation.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Enable support for selecting DTB within SPL based on EEPROM.
This will help to use single defconfig for both EVM and SK
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The AM64x SoC uses a central Device Management and Security Controller
(DMSC) processor that manages all the low-level device controls
including the system-wide SoC reset. The system-wide reset is managed
through the system reset driver.
Add a sysreset controller node as a child of the dmsc node to enable
the "reset" command from U-Boot prompt for the K3 AM642 SK.
Signed-off-by: Suman Anna <s-anna@ti.com>
The AM64x SoC uses a central Device Management and Security Controller
(DMSC) processor that manages all the low-level device controls
including the system-wide SoC reset. The system-wide reset is managed
through the system reset driver.
Add a sysreset controller node as a child of the dmsc node to enable
the "reset" command from U-Boot prompt for the K3 AM642 EVM.
Signed-off-by: Suman Anna <s-anna@ti.com>
The AM654 IDK daughter card supports few additional peripherals
like MCAN and 4 ICSSG Ethernet ports. The ICSSG IP is different
between the two AM65x Silicon Revisions SR1.0 and SR2.0, and so
warrants a separate overlay file when using on top of a AM654
base board populated with a SR1.0 silicon.
Add a new k3-am654-idk-sr1.dts overlay file, which includes the
k3-am654-idk.dts overlay file. The built overlays are identical
for now, but will diverge after ICSSG Ethernet support is added.
This fixes the following warning currently seen in A53 SPL on
AM65x EVMs with SR1.0 after the board logic is fixed up to pick
the separate overlay for kernel in commit ba961d78ac16 ("board:
ti: am65x: Use different overlay for IDK with SR1.0 EVM")
"cannot find image node 'k3-am654-idk-sr1': -1"
Signed-off-by: Suman Anna <s-anna@ti.com>
The AM654 IDK daughter card supports few additional peripherals
like MCAN and 4 ICSSG Ethernet ports. Add a new initial overlay
file, k3-am654-idk.dts, for this daughter card. This overlay file
will be be used with the standard AM654 EVM board. The overlay file
is currently empty and differs from the equivalent Linux kernel dts
overlay file as there is no required MCAN support in U-Boot, and
the ICSSG Ethernet support is not yet available.
This fixes the following warning currently seen in A53 SPL,
"cannot find image node 'k3-am654-idk': -1"
Signed-off-by: Suman Anna <s-anna@ti.com>
Add DT nodes to enable S28HS512T OSPI flash on the SK board.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
AM64 EVM has a S28HS512T flash. Add DT nodes for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
AM64 SoC has a Flash SubSystem with an OSPI controller within. Add DT
entries for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
commit 1d4e8a15d2fa21548250ad9acc3d13706e140e4b upstream.
Since commit 6239cc8c4e ("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts
into U-Boot") ranges have been added to CPSW node which results in
U-Boot CPSW driver failing to acquire phy_gmii_sel register range and
thus failing to configure GMII mode correctly.
Fix this by deleting ranges in -u-boot-dtsi just like its done for other
K3 platforms.
Fixes: 6239cc8c4e ("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Fix the clock names in USB device tree node.
Fixes: 3092efc090 ("arm: dts: k3-am64-main: Add USB DT nodes")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
This fixes the following warning at boot.
"cannot find image node 'k3-am654-pcie-usb3': -1"
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Add support for PCIe 2 lane with USB 2.0 daughter card.
Only PCIe support is added at this time. Patch is based on
work by Kishon Vijay Abraham I <kishon@ti.com> in Linux kernel.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
J7200 ROM supports booting from xSPI compliant flash. Detect if ROM
booted from xSPI bootmode and map that to BOOT_DEVICE_SPI
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Enable Octal DTR mode and PHY mode. Use the frequency of 25MHz because
that is what Octal DTR mode has been tested with.
The PHY partition is added in U-Boot specific dtsi because it is not
currently required by Kernel so it will make it easier to sync with
Kernel.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Enable Octal DTR mode and PHY mode. Use the frequency of 25MHz because
that is what Octal DTR mode has been tested with.
The PHY partition is added in U-Boot specific dtsi because it is not
currently required by Kernel so it will make it easier to sync with
Kernel.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its nodes to allow using SPI flashes.
The PHY partition is added in U-Boot specific dtsi because it is not
currently required by Kernel so it will make it easier to sync with
Kernel.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
A Wilink wireless device is connected to MMCSD0 subsystem and is not
supported in U-Boot. Therefore, disable main_sdhci0 device tree node in
U-Boot.
If main_sdhci0 device tree node is disabled then the the index if
main_sdhci1 node becomes 0 which leads to break in boot flow. Therefore,
add an alias to fix the index to 1.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
In function fdt_find_and_setprop(), argument "len" denotes the length of
the new property value only, not accumulated sum of lengths of property
name and property value. Therefore, fix it to the correct length of string
"host", which is 4.
Fixes: e130468298 ("arm: mach-k3: am642_init: Do USB fixups to facilitate host and device boot modes")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju
Gowtham Tammana
Lokesh Vutla
Roger Quadros
Kevin Scholz
Keerthy
Sinthu Raja
Vignesh Raghavendra
Suman Anna
Kishon Vijay Abraham I
Pratyush Yadav