Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Android build use different tool chain(gcc 4.9) with yocto(gcc 6.2),
'for' loop initial declarations are not supported in C90, define the
variable first before use it.
Test: build pass for imx8mm_evk.
Change-Id: Idf9a9f21626a02e2e679d2e74410378cd143c3f1
Signed-off-by: Luo Ji <ji.luo@nxp.com>
the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.
the same method can be use for DDR4. will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
Bai Ping
Luo Ji