Commit Graph

6 Commits

Author SHA1 Message Date
Breno Matheus Lima 656d8da9d2 doc: Remove duplicated documentation directory
Commit ad7061ed74 ("doc: Move device tree bindings documentation to
 doc/device-tree-bindings") moved all device tree binding documentation
to doc/device-tree-bindings directory.

The current U-Boot project still have two documentation directories:

- doc/
- Documentation/

Move all documentation and sphinx files to doc directory so all content
can be in a common place.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
2019-06-20 10:57:08 -04:00
Patrick Delaunay 3a29afcbbf doc: binding: rename directory ram to memory-controller
Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller

PS: the drivers using RAM u-class should be associated with
    this binding directory

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-28 14:21:46 -05:00
Lokesh Vutla 06bda1259f ram: Introduce K3 AM654 DDR Sub System driver
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-16 16:51:58 -05:00
Patrick Delaunay e70f70aa65 ram: stm32mp1: add driver
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:21 -04:00
Patrice Chotard f303aaf21b ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:15 -04:00
Vikas Manocha fd198ee1a8 ARM: DT: stm32f7: add sdram pin contol node
Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:03 -04:00