u-boot

Commit Graph

Author	SHA1	Message	Date
Masahiro Yamada	6c22742d3d	ARM: uniphier: enable SSC for DPLL (DRAM PLL) on LD11 SoC For Electro-Magnetic Compatibility test. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>	2016-10-10 10:03:23 +09:00
Masahiro Yamada	c72f4d4c2e	ARM: uniphier: add PLL init code for LD11 SoC - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>	2016-09-23 01:00:23 +09:00

Author

SHA1

Message

Date

Masahiro Yamada

6c22742d3d

ARM: uniphier: enable SSC for DPLL (DRAM PLL) on LD11 SoC

For Electro-Magnetic Compatibility test.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

2016-10-10 10:03:23 +09:00

Masahiro Yamada

c72f4d4c2e

ARM: uniphier: add PLL init code for LD11 SoC

- Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

2016-09-23 01:00:23 +09:00

2 Commits