u-boot

Commit Graph

Author	SHA1	Message	Date
York Sun	f80d6472b4	driver/ddr/fsl: Fix DDR4 driver When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>	2014-09-25 08:36:20 -07:00
York Sun	8340e7ac86	driver/ddr: Fix DDR4 driver for ARM Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>	2014-07-22 16:25:54 -07:00
York Sun	34e026f9b1	driver/ddr/fsl: Add DDR4 support to Freescale DDR driver Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>	2014-04-22 17:58:48 -07:00

Author

SHA1

Message

Date

York Sun

f80d6472b4

driver/ddr/fsl: Fix DDR4 driver

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>

2014-09-25 08:36:20 -07:00

York Sun

8340e7ac86

driver/ddr: Fix DDR4 driver for ARM

Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>

2014-07-22 16:25:54 -07:00

York Sun

34e026f9b1

driver/ddr/fsl: Add DDR4 support to Freescale DDR driver

Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>

2014-04-22 17:58:48 -07:00

3 Commits