u-boot

Commit Graph

Author	SHA1	Message	Date
Simon Glass	f1683aa73c	board_f: Rename initdram() to dram_init() This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>	2017-04-13 09:40:57 -04:00
Purna Chandra Mandal	9ffa7a35ef	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32. This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>	2016-02-01 22:14:01 +01:00

Author

SHA1

Message

Date

Simon Glass

f1683aa73c

board_f: Rename initdram() to dram_init()

This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>

2017-04-13 09:40:57 -04:00

Purna Chandra Mandal

9ffa7a35ef

drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

2016-02-01 22:14:01 +01:00

2 Commits