161 lines
3.3 KiB
C
161 lines
3.3 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#ifdef CONFIG_S3C24X0
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#include <asm/io.h>
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#include <asm/arch/s3c24x0_cpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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int timer_init(void)
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{
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struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
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ulong tmr;
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/* use PWM Timer 4 because it has no output */
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/* prescaler for Timer 4 is 16 */
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writel(0x0f00, &timers->tcfg0);
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if (gd->arch.tbu == 0) {
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/*
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* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
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* (default) and prescaler = 16. Should be 10390
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* @33.25MHz and 15625 @ 50 MHz
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*/
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gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
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gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
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}
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/* load value for 10 ms timeout */
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writel(gd->arch.tbu, &timers->tcntb4);
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/* auto load, manual update of timer 4 */
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tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
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writel(tmr, &timers->tcon);
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/* auto load, start timer 4 */
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tmr = (tmr & ~0x0700000) | 0x0500000;
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writel(tmr, &timers->tcon);
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gd->arch.lastinc = 0;
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gd->arch.tbl = 0;
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return 0;
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}
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/*
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* timer without interrupts
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*/
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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void __udelay (unsigned long usec)
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{
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ulong tmo;
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ulong start = get_ticks();
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tmo = usec / 1000;
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tmo *= (gd->arch.tbu * 100);
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tmo /= 1000;
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while ((ulong) (get_ticks() - start) < tmo)
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/*NOP*/;
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}
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ulong get_timer_masked(void)
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{
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ulong tmr = get_ticks();
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return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
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}
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void udelay_masked(unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= (gd->arch.tbu * 100);
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tmo /= 1000;
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} else {
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tmo = usec * (gd->arch.tbu * 100);
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tmo /= (1000 * 1000);
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}
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endtime = get_ticks() + tmo;
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do {
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ulong now = get_ticks();
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diff = endtime - now;
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} while (diff >= 0);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
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ulong now = readl(&timers->tcnto4) & 0xffff;
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if (gd->arch.lastinc >= now) {
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/* normal mode */
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gd->arch.tbl += gd->arch.lastinc - now;
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} else {
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/* we have an overflow ... */
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gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
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}
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gd->arch.lastinc = now;
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return gd->arch.tbl;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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/*
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* reset the cpu by setting up the watchdog timer and let him time out
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*/
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void reset_cpu(ulong ignored)
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{
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struct s3c24x0_watchdog *watchdog;
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watchdog = s3c24x0_get_base_watchdog();
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/* Disable watchdog */
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writel(0x0000, &watchdog->wtcon);
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/* Initialize watchdog timer count register */
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writel(0x0001, &watchdog->wtcnt);
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/* Enable watchdog timer; assert reset at timer timeout */
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writel(0x0021, &watchdog->wtcon);
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while (1)
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/* loop forever and wait for reset to happen */;
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/*NOTREACHED*/
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}
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#endif /* CONFIG_S3C24X0 */
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