323 lines
12 KiB
C
323 lines
12 KiB
C
/*
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* LayerScape Internal Memory Map
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
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#define __ARCH_FSL_LSCH3_IMMAP_H_
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
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#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
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#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
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#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
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#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
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#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
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#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
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#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
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#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
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#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
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#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
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0x18A0)
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#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
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#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
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#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
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#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
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/* SP (Cortex-A5) related */
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#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
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#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
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#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
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#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
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(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
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#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
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(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
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#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
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#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
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#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
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#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
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#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
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#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
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#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
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#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
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#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
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#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
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/* TZ Address Space Controller Definitions */
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#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
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#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
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#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
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#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
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#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
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#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
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#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
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#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
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#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
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#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
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#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
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#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
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#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
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/* SATA */
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#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
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#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
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/* SFP */
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#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
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/* SEC */
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
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#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
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#define CONFIG_SYS_FSL_SEC_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
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#define CONFIG_SYS_FSL_JR0_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
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/* Security Monitor */
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#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
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/* MMU 500 */
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#define SMMU_SCR0 (SMMU_BASE + 0x0)
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#define SMMU_SCR1 (SMMU_BASE + 0x4)
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#define SMMU_SCR2 (SMMU_BASE + 0x8)
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#define SMMU_SACR (SMMU_BASE + 0x10)
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#define SMMU_IDR0 (SMMU_BASE + 0x20)
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#define SMMU_IDR1 (SMMU_BASE + 0x24)
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#define SMMU_NSCR0 (SMMU_BASE + 0x400)
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#define SMMU_NSCR2 (SMMU_BASE + 0x408)
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#define SMMU_NSACR (SMMU_BASE + 0x410)
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#define SCR0_CLIENTPD_MASK 0x00000001
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#define SCR0_USFCFG_MASK 0x00000400
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/* PCIe */
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
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#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
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#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
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#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
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/* LUT registers */
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#define PCIE_LUT_BASE 0x80000
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#define PCIE_LUT_LCTRL0 0x7F8
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#define PCIE_LUT_DBG 0x7FC
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#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
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#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
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#define PCIE_LUT_ENABLE (1 << 31)
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#define PCIE_LUT_ENTRY_COUNT 32
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/* Device Configuration */
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#define DCFG_BASE 0x01e00000
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#define DCFG_PORSR1 0x000
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#define DCFG_PORSR1_RCW_SRC 0xff800000
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#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
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#define DCFG_RCWSR13 0x130
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#define DCFG_RCWSR13_DSPI (0 << 8)
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#define DCFG_DCSR_BASE 0X700100000ULL
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#define DCFG_DCSR_PORCR1 0x000
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/* Interrupt Sampling Control */
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#define ISC_BASE 0x01F70000
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#define IRQCR_OFFSET 0x14
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/* Supplemental Configuration */
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#define SCFG_BASE 0x01fc0000
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#define SCFG_USB3PRM1CR 0x000
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#define TP_ITYP_AV 0x00000001 /* Initiator available */
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#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
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#define TP_ITYP_TYPE_ARM 0x0
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#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
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#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
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#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
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#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
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#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
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#define TY_ITYP_VER_A7 0x1
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#define TY_ITYP_VER_A53 0x2
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#define TY_ITYP_VER_A57 0x3
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#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
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#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
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#define TP_INIT_PER_CLUSTER 4
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/* This is chassis generation 3 */
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struct sys_info {
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unsigned long freq_processor[CONFIG_MAX_CPUS];
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unsigned long freq_systembus;
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unsigned long freq_ddrbus;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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unsigned long freq_ddrbus2;
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#endif
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unsigned long freq_localbus;
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unsigned long freq_qe;
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#ifdef CONFIG_SYS_DPAA_FMAN
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unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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unsigned long freq_qman;
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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unsigned long freq_pme;
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#endif
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};
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/* Global Utilities Block */
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struct ccsr_gur {
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u32 porsr1; /* POR status 1 */
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u32 porsr2; /* POR status 2 */
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u8 res_008[0x20-0x8];
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u32 gpporcr1; /* General-purpose POR configuration */
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u32 gpporcr2; /* General-purpose POR configuration 2 */
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#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
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#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
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#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
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#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
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u32 dcfg_fusesr; /* Fuse status register */
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u32 gpporcr3;
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u32 gpporcr4;
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u8 res_034[0x70-0x34];
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u32 devdisr; /* Device disable control */
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u32 devdisr2; /* Device disable control 2 */
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u32 devdisr3; /* Device disable control 3 */
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u32 devdisr4; /* Device disable control 4 */
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u32 devdisr5; /* Device disable control 5 */
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u32 devdisr6; /* Device disable control 6 */
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u32 devdisr7; /* Device disable control 7 */
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#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
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#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
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#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
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#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
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#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
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#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
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#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
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#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
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#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
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#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
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#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
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#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
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#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
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#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
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u8 res_08c[0x90-0x8c];
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u32 coredisru; /* uppper portion for support of 64 cores */
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u32 coredisrl; /* lower portion for support of 64 cores */
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u8 res_098[0xa0-0x98];
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u32 pvr; /* Processor version */
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u32 svr; /* System version */
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u32 mvr; /* Manufacturing version */
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u8 res_0ac[0x100-0xac];
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u32 rcwsr[32]; /* Reset control word status */
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#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
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#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
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#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
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#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
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#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
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#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
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#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
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#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
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#define RCW_SB_EN_REG_INDEX 9
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#define RCW_SB_EN_MASK 0x00000400
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u8 res_180[0x200-0x180];
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u32 scratchrw[32]; /* Scratch Read/Write */
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u8 res_280[0x300-0x280];
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u32 scratchw1r[4]; /* Scratch Read (Write once) */
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u8 res_310[0x400-0x310];
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u32 bootlocptrl; /* Boot location pointer low-order addr */
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u32 bootlocptrh; /* Boot location pointer high-order addr */
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u8 res_408[0x500-0x408];
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u8 res_500[0x740-0x500]; /* add more registers when needed */
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u32 tp_ityp[64]; /* Topology Initiator Type Register */
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struct {
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u32 upper;
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u32 lower;
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} tp_cluster[3]; /* Core Cluster n Topology Register */
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u8 res_858[0x1000-0x858];
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};
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struct ccsr_clk_cluster_group {
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struct {
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u8 res_00[0x10];
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u32 csr;
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u8 res_14[0x20-0x14];
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} hwncsr[3];
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u8 res_60[0x80-0x60];
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struct {
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u32 gsr;
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u8 res_84[0xa0-0x84];
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} pllngsr[3];
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u8 res_e0[0x100-0xe0];
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};
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struct ccsr_clk_ctrl {
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struct {
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u32 csr; /* core cluster n clock control status */
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u8 res_04[0x20-0x04];
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} clkcncsr[8];
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};
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struct ccsr_reset {
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u32 rstcr; /* 0x000 */
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u32 rstcrsp; /* 0x004 */
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u8 res_008[0x10-0x08]; /* 0x008 */
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u32 rstrqmr1; /* 0x010 */
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u32 rstrqmr2; /* 0x014 */
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u32 rstrqsr1; /* 0x018 */
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u32 rstrqsr2; /* 0x01c */
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u32 rstrqwdtmrl; /* 0x020 */
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u32 rstrqwdtmru; /* 0x024 */
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u8 res_028[0x30-0x28]; /* 0x028 */
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u32 rstrqwdtsrl; /* 0x030 */
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u32 rstrqwdtsru; /* 0x034 */
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u8 res_038[0x60-0x38]; /* 0x038 */
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u32 brrl; /* 0x060 */
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u32 brru; /* 0x064 */
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u8 res_068[0x80-0x68]; /* 0x068 */
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u32 pirset; /* 0x080 */
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u32 pirclr; /* 0x084 */
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u8 res_088[0x90-0x88]; /* 0x088 */
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u32 brcorenbr; /* 0x090 */
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u8 res_094[0x100-0x94]; /* 0x094 */
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u32 rcw_reqr; /* 0x100 */
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u32 rcw_completion; /* 0x104 */
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u8 res_108[0x110-0x108]; /* 0x108 */
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u32 pbi_reqr; /* 0x110 */
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u32 pbi_completion; /* 0x114 */
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u8 res_118[0xa00-0x118]; /* 0x118 */
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u32 qmbm_warmrst; /* 0xa00 */
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u32 soc_warmrst; /* 0xa04 */
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u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
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u32 ip_rev1; /* 0xbf8 */
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u32 ip_rev2; /* 0xbfc */
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};
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#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
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