5da847a4fa
FEC has some clock settings inside DSC GPR. Kernel configures them,
but u-boot not. So when doing partition reset, the GPR keeps the value
from kernel, and cause clock issue to u-boot FEC: kernel enables the
divclk in GPR and set the clock slice to 250Mhz, u-boot configures the
clock slice to 125Mhz, the divclk causes the RGMII TX CLK to 62.5Mhz.
Fix the issue by aligning the GPR and clock slice settings with kernel
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit
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