259 lines
10 KiB
C
259 lines
10 KiB
C
/*
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* Copyright (c) 2012-2016, Freescale Semiconductor, Inc.
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* All rights reserved.
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* Copyright 2018 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CAAM_INTERNAL_H__
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#define __CAAM_INTERNAL_H__
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/* 4kbyte pages */
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#define CAAM_SEC_RAM_START_ADDR CAAM_ARB_BASE_ADDR
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#define SEC_MEM_PAGE0 CAAM_SEC_RAM_START_ADDR
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#define SEC_MEM_PAGE1 (CAAM_SEC_RAM_START_ADDR + 0x1000)
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#define SEC_MEM_PAGE2 (CAAM_SEC_RAM_START_ADDR + 0x2000)
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#define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000)
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/* Configuration and special key registers */
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#define CAAM_MCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x0004)
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#define CAAM_SCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x000c)
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#define CAAM_JR0MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0010)
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#define CAAM_JR1MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0018)
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#define CAAM_DECORR (CONFIG_SYS_FSL_SEC_ADDR + 0x009c)
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#define CAAM_DECO0MID (CONFIG_SYS_FSL_SEC_ADDR + 0x00a0)
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#define CAAM_DAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0120)
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#define CAAM_DRR (CONFIG_SYS_FSL_SEC_ADDR + 0x0124)
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#define CAAM_JDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0400)
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#define CAAM_TDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0420)
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#define CAAM_TDSKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0440)
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#define CAAM_SKNR (CONFIG_SYS_FSL_SEC_ADDR + 0x04e0)
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#define CAAM_SMSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FB4)
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#define CAAM_STA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FD4)
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#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
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#define CAAM_CHAVID_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x0FEC)
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#define CAAM_FAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC0)
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#define CAAM_FAMR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC8)
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#define CAAM_FADR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FCC)
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/* RNG registers */
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#define CAAM_RTMCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0600)
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#define CAAM_RTSCMISC (CONFIG_SYS_FSL_SEC_ADDR + 0x0604)
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#define CAAM_RTPKRRNG (CONFIG_SYS_FSL_SEC_ADDR + 0x0608)
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#define CAAM_RTPKRMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x060C)
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#define CAAM_RTSDCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0610)
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#define CAAM_RTFRQMIN (CONFIG_SYS_FSL_SEC_ADDR + 0x0618)
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#define CAAM_RTFRQMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x061C)
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#define CAAM_RTSCML (CONFIG_SYS_FSL_SEC_ADDR + 0x0620)
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#define CAAM_RTSCR1L (CONFIG_SYS_FSL_SEC_ADDR + 0x0624)
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#define CAAM_RTSCR2L (CONFIG_SYS_FSL_SEC_ADDR + 0x0628)
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#define CAAM_RTSCR3L (CONFIG_SYS_FSL_SEC_ADDR + 0x062C)
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#define CAAM_RTSCR4L (CONFIG_SYS_FSL_SEC_ADDR + 0x0630)
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#define CAAM_RTSCR5L (CONFIG_SYS_FSL_SEC_ADDR + 0x0634)
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#define CAAM_RTSCR6PL (CONFIG_SYS_FSL_SEC_ADDR + 0x0638)
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#define CAAM_RTSTATUS (CONFIG_SYS_FSL_SEC_ADDR + 0x063C)
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#define CAAM_RDSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x06C0)
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/* Job Ring 0 registers */
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#define CAAM_IRBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1004)
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#define CAAM_IRSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x100c)
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#define CAAM_IRSAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1014)
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#define CAAM_IRJAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x101c)
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#define CAAM_ORBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1024)
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#define CAAM_ORSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x102c)
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#define CAAM_ORJRR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1034)
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#define CAAM_ORSFR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x103c)
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#define CAAM_JRSTAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1044)
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#define CAAM_JRINTR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x104c)
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#define CAAM_JRCFGR0_MS (CONFIG_SYS_FSL_SEC_ADDR + 0x1050)
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#define CAAM_JRCFGR0_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x1054)
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#define CAAM_IRRIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x105c)
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#define CAAM_ORWIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1064)
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#define CAAM_JRCR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x106c)
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#define CAAM_SMCJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10f4)
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#define CAAM_SMCSJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10fc)
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#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
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#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
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#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
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#define CAAM_SMAPJR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1114)
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#define CAAM_SMAG2JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1118)
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#define CAAM_SMAG1JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x111c)
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#define CAAM_SMPO (CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc)
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#define DESC_MAX_SIZE (0x40) /* Descriptor max size */
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#define JRCFG_LS_IMSK (0x01) /* Interrupt Mask */
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#define JR_MID (0x02) /* Matches ROM configuration */
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#define KS_G1 BIT(JR_MID) /* CAAM only */
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#define PERM (0x0000B008) /* Clear on release, lock SMAP,
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* lock SMAG and group 1 Blob
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*/
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#define CMD_PAGE_ALLOC (0x1)
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#define CMD_PAGE_DEALLOC (0x2)
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#define CMD_PART_DEALLOC (0x3)
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#define CMD_INQUIRY (0x5)
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#define PAGE(x) (x << 16)
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#define PARTITION(x) (x << 8)
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#define SMCSJR_AERR (3 << 12)
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#define SMCSJR_CERR (3 << 14)
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#define CMD_COMPLETE (3 << 14)
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#define SMCSJR_PO (3 << 6)
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#define PAGE_AVAILABLE (0)
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#define PAGE_OWNED (3 << 6)
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#define PARTITION_OWNER(x) (0x3 << (x*2))
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#define CAAM_BUSY_MASK (0x00000001) /* BUSY from status reg */
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#define CAAM_IDLE_MASK (0x00000002) /* IDLE from status reg */
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#define CAAM_MCFGR_SWRST BIT(31) /* CAAM SW reset */
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#define CAAM_MCFGR_DMARST BIT(28) /* CAAM DMA reset */
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#define JOB_RING_ENTRIES (1)
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#define JOB_RING_STS (0xF << 28)
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/** OSC_DIV in RNG trim fuses */
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#define RNG_TRIM_OSC_DIV (0)
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/** ENT_DLY multiplier in RNG trim fuses */
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#define TRNG_SDCTL_ENT_DLY_MIN (3200)
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#define TRNG_SDCTL_ENT_DLY_MAX (4800)
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#define RTMCTL_PGM BIT(16)
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#define RTMCTL_ERR BIT(12)
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#define RTMCTL_RST BIT(6)
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#define RTMCTL_ACC BIT(5)
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#define RDSTA_IF0 (1)
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#define RDSTA_IF1 (2)
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#define RDSTA_SKVN BIT(30)
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#define JRCR_RESET (1)
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#define RTMCTL_FCT_FAIL BIT(8)
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#define BS_TRNG_ENT_DLY (16)
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#define BM_TRNG_ENT_DLY (0xffff << BS_TRNG_ENT_DLY)
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#define BM_TRNG_SAMP_MODE (3)
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#define TRNG_SAMP_MODE_RAW_ES_SC (1)
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#define BS_JRINTR_HALT (2)
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#define BM_JRINTR_HALT (0x3 << BS_JRINTR_HALT)
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#define JRINTR_HALT_ONGOING (0x1 << BS_JRINTR_HALT)
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#define JRINTR_HALT_DONE (0x2 << BS_JRINTR_HALT)
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#define JRINTR_JRI (0x1)
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#define BS_JRCFGR_LS_ICTT (16)
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#define BM_JRCFGR_LS_ICTT (0xFFFF << BS_JRCFGR_LS_ICTT)
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#define BS_JRCFGR_LS_ICDCT (8)
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#define BM_JRCFGR_LS_ICDCT (0xFF << BS_JRCFGR_LS_ICDCT)
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#define BS_JRCFGR_LS_ICEN (1)
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#define BM_JRCFGR_LS_ICEN (0x1 << BS_JRCFGR_LS_ICEN)
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#define BS_JRCFGR_LS_IMSK (0)
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#define BM_JRCFGR_LS_IMSK (0x1 << BS_JRCFGR_LS_IMSK)
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#define BS_CHAVID_LS_RNGVID (16)
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#define BM_CHAVID_LS_RNGVID (0xF << BS_CHAVID_LS_RNGVID)
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#define BS_MCFGR_WDE (30)
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#define BM_MCFGR_WDE (0x1 << BS_MCFGR_WDE)
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typedef enum {
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PAGE_0,
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PAGE_1,
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PAGE_2,
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PAGE_3,
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} page_num_e;
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typedef enum {
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PARTITION_0,
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PARTITION_1,
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PARTITION_2,
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PARTITION_3,
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PARTITION_4,
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PARTITION_5,
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PARTITION_6,
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PARTITION_7,
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} partition_num_e;
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/*
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* Local defines
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*/
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/* arm v7 need 64 align */
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#define ALIGN_MASK ~(ARCH_DMA_MINALIGN - 1)
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/* caam dma and pointer conversion for arm and arm64 architectures */
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#ifdef CONFIG_IMX_CONFIG
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#define PTR2CAAMDMA(x) (u32)((uintptr_t)(x) & 0xffffffff)
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#define CAAMDMA2PTR(x) (uintptr_t)((x) & 0xffffffff)
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#else
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#define PTR2CAAMDMA(x) (uintptr_t)(x)
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#define CAAMDMA2PTR(x) (uintptr_t)(x)
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#endif
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#define RING_EARLY_INIT (0x01)
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#define RING_RELOC_INIT (0x02)
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#define CAAM_HDR_CTYPE (0x16u << 27)
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#define CAAM_HDR_ONE BIT(23)
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#define CAAM_HDR_START_INDEX(x) (((x) & 0x3F) << 16)
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#define CAAM_HDR_DESCLEN(x) ((x) & 0x3F)
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#define CAAM_PROTOP_CTYPE (0x10u << 27)
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/* State Handle */
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#define BS_ALGO_RNG_SH (4)
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#define BM_ALGO_RNG_SH (0x3 << BS_ALGO_RNG_SH)
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#define ALGO_RNG_SH(id) (((id) << BS_ALGO_RNG_SH) & BM_ALGO_RNG_SH)
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/* Secure Key */
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#define BS_ALGO_RNG_SK (12)
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#define BM_ALGO_RNG_SK BIT(BS_ALGO_RNG_SK)
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/* State */
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#define BS_ALGO_RNG_AS (2)
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#define BM_ALGO_RNG_AS (0x3 << BS_ALGO_RNG_AS)
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#define ALGO_RNG_GENERATE (0x0 << BS_ALGO_RNG_AS)
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#define ALGO_RNG_INSTANTIATE BIT(BS_ALGO_RNG_AS)
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#define CAAM_C1_RNG ((0x50 << 16) | (2 << 24))
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#define BS_JUMP_LOCAL_OFFSET (0)
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#define BM_JUMP_LOCAL_OFFSET (0xFF << BS_JUMP_LOCAL_OFFSET)
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#define CAAM_C1_JUMP ((0x14u << 27) | (1 << 25))
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#define CAAM_JUMP_LOCAL (0 << 20)
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#define CAAM_JUMP_TST_ALL_COND_TRUE (0 << 16)
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#define CAAM_JUMP_OFFSET(off) (((off) << BS_JUMP_LOCAL_OFFSET) \
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& BM_JUMP_LOCAL_OFFSET)
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#define CAAM_C0_LOAD_IMM ((0x2 << 27) | (1 << 23))
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#define CAAM_DST_CLEAR_WRITTEN (0x8 << 16)
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#define RNG_DESC_SH0_SIZE (ARRAY_SIZE(rng_inst_sh0_desc))
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#define RNG_DESC_SH1_SIZE (ARRAY_SIZE(rng_inst_sh1_desc))
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#define RNG_DESC_KEYS_SIZE (ARRAY_SIZE(rng_inst_load_keys))
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#define RNG_DESC_MAX_SIZE (RNG_DESC_SH0_SIZE + \
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RNG_DESC_SH1_SIZE + \
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RNG_DESC_KEYS_SIZE)
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#define CAAM_PAD_LEN 48
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#endif /* __CAAM_INTERNAL_H__ */
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