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Bai Ping 71398b89a0 MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip 
Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 566b798213)
 		2018-11-20 18:28:22 +08:00
..
Kconfig MLK-18431-02: add a more generic dram init flow for imx8m 2018-08-05 22:36:07 -07:00
Makefile MLK-19777-03: imx8mm_evk: Optimize the ddr4 init flow 2018-10-01 17:25:25 +08:00
ddr4_init.c MLK-19907 imx8m: ddr4: Update the refresh_mode setting 2018-10-12 16:28:56 +08:00
ddrphy_train.c MLK-19777-01: imx8mm: rename the lpddr4_ddrphy_train file 2018-10-01 17:25:24 +08:00
ddrphy_utils.c MLK-20163-02 imx8m: ddr: update the dram driver for i.MX8M 2018-11-02 20:50:11 -05:00
helper.c MLK-20163-02 imx8m: ddr: update the dram driver for i.MX8M 2018-11-02 20:50:11 -05:00
lpddr4_init.c MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip 2018-11-20 18:28:22 +08:00