345 lines
7.8 KiB
C
345 lines
7.8 KiB
C
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/immap.h>
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struct cf_spi_slave {
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struct spi_slave slave;
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uint baudrate;
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int charbit;
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};
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extern void cfspi_port_conf(void);
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extern int cfspi_claim_bus(uint bus, uint cs);
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extern void cfspi_release_bus(uint bus, uint cs);
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SPI_IDLE_VAL
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#if defined(CONFIG_SPI_MMC)
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#define CONFIG_SPI_IDLE_VAL 0xFFFF
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#else
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#define CONFIG_SPI_IDLE_VAL 0x0
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#endif
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#endif
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#if defined(CONFIG_CF_DSPI)
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/* DSPI specific mode */
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#define SPI_MODE_MOD 0x00200000
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#define SPI_DBLRATE 0x00100000
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static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct cf_spi_slave, slave);
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}
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static void cfspi_init(void)
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{
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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cfspi_port_conf(); /* port configuration */
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dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
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DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
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DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
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DSPI_MCR_CRXF | DSPI_MCR_CTXF;
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/* Default setting in platform configuration */
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#ifdef CONFIG_SYS_DSPI_CTAR0
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dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR1
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dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR2
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dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR3
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dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR4
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dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR5
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dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR6
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dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR7
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dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
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#endif
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}
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static void cfspi_tx(u32 ctrl, u16 data)
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{
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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while ((dspi->sr & 0x0000F000) >= 4) ;
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dspi->tfr = (ctrl | data);
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}
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static u16 cfspi_rx(void)
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{
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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while ((dspi->sr & 0x000000F0) == 0) ;
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return (dspi->rfr & 0xFFFF);
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}
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static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
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void *din, ulong flags)
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{
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struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
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u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
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u8 *spi_rd = NULL, *spi_wr = NULL;
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static u32 ctrl = 0;
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uint len = bitlen >> 3;
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if (cfslave->charbit == 16) {
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bitlen >>= 1;
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spi_wr16 = (u16 *) dout;
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spi_rd16 = (u16 *) din;
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} else {
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spi_wr = (u8 *) dout;
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spi_rd = (u8 *) din;
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}
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if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
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ctrl |= DSPI_TFR_CONT;
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ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
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if (len > 1) {
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int tmp_len = len - 1;
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while (tmp_len--) {
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if (dout != NULL) {
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if (cfslave->charbit == 16)
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cfspi_tx(ctrl, *spi_wr16++);
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else
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cfspi_tx(ctrl, *spi_wr++);
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cfspi_rx();
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}
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if (din != NULL) {
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cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
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if (cfslave->charbit == 16)
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*spi_rd16++ = cfspi_rx();
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else
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*spi_rd++ = cfspi_rx();
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}
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}
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len = 1; /* remaining byte */
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}
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if ((flags & SPI_XFER_END) == SPI_XFER_END)
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ctrl &= ~DSPI_TFR_CONT;
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if (len) {
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if (dout != NULL) {
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if (cfslave->charbit == 16)
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cfspi_tx(ctrl, *spi_wr16);
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else
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cfspi_tx(ctrl, *spi_wr);
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cfspi_rx();
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}
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if (din != NULL) {
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cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
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if (cfslave->charbit == 16)
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*spi_rd16 = cfspi_rx();
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else
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*spi_rd = cfspi_rx();
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}
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} else {
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/* dummy read */
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cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
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cfspi_rx();
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}
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return 0;
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}
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static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
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uint mode)
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{
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/*
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* bit definition for mode:
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* bit 31 - 28: Transfer size 3 to 16 bits
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* 27 - 26: PCS to SCK delay prescaler
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* 25 - 24: After SCK delay prescaler
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* 23 - 22: Delay after transfer prescaler
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* 21 : Allow overwrite for bit 31-22 and bit 20-8
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* 20 : Double baud rate
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* 19 - 16: PCS to SCK delay scaler
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* 15 - 12: After SCK delay scaler
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* 11 - 8: Delay after transfer scaler
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* 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
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*/
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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int prescaler[] = { 2, 3, 5, 7 };
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int scaler[] = {
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2, 4, 6, 8,
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16, 32, 64, 128,
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256, 512, 1024, 2048,
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4096, 8192, 16384, 32768
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};
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int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
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int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
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u32 bus_setup = 0;
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tmp = (prescaler[3] * scaler[15]);
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/* Maximum and minimum baudrate it can handle */
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if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
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(cfslave->baudrate < (gd->bus_clk / tmp))) {
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printf("Exceed baudrate limitation: Max %d - Min %d\n",
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(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
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return NULL;
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}
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/* Activate Double Baud when it exceed 1/4 the bus clk */
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if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
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(cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
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bus_setup |= DSPI_CTAR_DBR;
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dbr = 1;
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}
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if (mode & SPI_CPOL)
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bus_setup |= DSPI_CTAR_CPOL;
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if (mode & SPI_CPHA)
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bus_setup |= DSPI_CTAR_CPHA;
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if (mode & SPI_LSB_FIRST)
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bus_setup |= DSPI_CTAR_LSBFE;
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/* Overwrite default value set in platform configuration file */
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if (mode & SPI_MODE_MOD) {
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if ((mode & 0xF0000000) == 0)
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bus_setup |=
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dspi->ctar[cfslave->slave.bus] & 0x78000000;
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else
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bus_setup |= ((mode & 0xF0000000) >> 1);
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/*
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* Check to see if it is enabled by default in platform
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* config, or manual setting passed by mode parameter
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*/
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if (mode & SPI_DBLRATE) {
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bus_setup |= DSPI_CTAR_DBR;
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dbr = 1;
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}
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bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
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bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
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} else
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bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
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cfslave->charbit =
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((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
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0x78000000) ? 16 : 8;
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pbrcnt = sizeof(prescaler) / sizeof(int);
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brcnt = sizeof(scaler) / sizeof(int);
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/* baudrate calculation - to closer value, may not be exact match */
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for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
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baud_speed = gd->bus_clk / prescaler[i];
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for (j = 0; j < brcnt; j++) {
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tmp = (baud_speed / scaler[j]) * (1 + dbr);
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if (tmp > cfslave->baudrate)
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diff = tmp - cfslave->baudrate;
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else
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diff = cfslave->baudrate - tmp;
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if (diff < bestmatch) {
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bestmatch = diff;
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best_i = i;
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best_j = j;
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}
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}
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}
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bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
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dspi->ctar[cfslave->slave.bus] = bus_setup;
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return &cfslave->slave;
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}
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#endif /* CONFIG_CF_DSPI */
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#ifdef CONFIG_CMD_SPI
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
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return 1;
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else
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return 0;
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}
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void spi_init_f(void)
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{
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}
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void spi_init_r(void)
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{
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}
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void spi_init(void)
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{
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cfspi_init();
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct cf_spi_slave *cfslave;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
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if (!cfslave)
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return NULL;
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cfslave->baudrate = max_hz;
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/* specific setup */
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return cfspi_setup_slave(cfslave, mode);
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
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free(cfslave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return cfspi_claim_bus(slave->bus, slave->cs);
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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cfspi_release_bus(slave->bus, slave->cs);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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return cfspi_xfer(slave, bitlen, dout, din, flags);
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}
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#endif /* CONFIG_CMD_SPI */
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