605 lines
19 KiB
C
605 lines
19 KiB
C
/*
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* cpu.h
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*
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* AM33xx specific header file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _AM33XX_CPU_H
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#define _AM33XX_CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#include <asm/arch/hardware.h>
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#define CL_BIT(x) (0 << x)
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/* Timer register bits */
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#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
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#define TCLR_AR BIT(1) /* Auto reload */
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#define TCLR_PRE BIT(5) /* Pre-scaler enable */
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#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
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#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
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#define TCLR_CE BIT(6) /* compare mode enable */
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#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
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#define TCLR_TCM BIT(8) /* edge detection of input pin*/
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#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
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#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
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#define TCLR_CAPTMODE BIT(13) /* capture mode */
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#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
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#define TCFG_RESET BIT(0) /* software reset */
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#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
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#define TCFG_IDLEMOD_SHIFT (2) /* power management */
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/* device type */
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#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* cpu-id for AM33XX and TI81XX family */
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#define AM335X 0xB944
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#define TI81XX 0xB81E
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#define DEVICE_ID (CTRL_BASE + 0x0600)
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#define DEVICE_ID_MASK 0x1FFF
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/* MPU max frequencies */
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#define AM335X_ZCZ_300 0x1FEF
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#define AM335X_ZCZ_600 0x1FAF
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#define AM335X_ZCZ_720 0x1F2F
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#define AM335X_ZCZ_800 0x1E2F
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#define AM335X_ZCZ_1000 0x1C2F
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#define AM335X_ZCE_300 0x1FDF
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#define AM335X_ZCE_600 0x1F9F
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/* This gives the status of the boot mode pins on the evm */
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#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
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| BIT(3) | BIT(4))
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#define PRM_RSTCTRL_RESET 0x01
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#define PRM_RSTST_WARM_RESET_MASK 0x232
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/*
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* Watchdog:
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* Using the prescaler, the OMAP watchdog could go for many
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* months before firing. These limits work without scaling,
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* with the 60 second default assumed by most tools and docs.
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*/
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#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
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#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
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#define TIMER_MARGIN_MIN 1
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#define PTV 0 /* prescale */
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#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
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#define WDT_WWPS_PEND_WCLR BIT(0)
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#define WDT_WWPS_PEND_WLDR BIT(2)
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#define WDT_WWPS_PEND_WTGR BIT(3)
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#define WDT_WWPS_PEND_WSPR BIT(4)
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#define WDT_WCLR_PRE BIT(5)
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#define WDT_WCLR_PTV_OFF 2
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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#ifndef CONFIG_AM43XX
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/* Encapsulating core pll registers */
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struct cm_wkuppll {
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unsigned int wkclkstctrl; /* offset 0x00 */
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unsigned int wkctrlclkctrl; /* offset 0x04 */
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unsigned int wkgpio0clkctrl; /* offset 0x08 */
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unsigned int wkl4wkclkctrl; /* offset 0x0c */
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unsigned int timer0clkctrl; /* offset 0x10 */
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unsigned int resv2[3];
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unsigned int idlestdpllmpu; /* offset 0x20 */
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unsigned int resv3[2];
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unsigned int clkseldpllmpu; /* offset 0x2c */
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unsigned int resv4[1];
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unsigned int idlestdpllddr; /* offset 0x34 */
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unsigned int resv5[2];
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unsigned int clkseldpllddr; /* offset 0x40 */
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unsigned int resv6[4];
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unsigned int clkseldplldisp; /* offset 0x54 */
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unsigned int resv7[1];
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unsigned int idlestdpllcore; /* offset 0x5c */
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unsigned int resv8[2];
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unsigned int clkseldpllcore; /* offset 0x68 */
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unsigned int resv9[1];
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unsigned int idlestdpllper; /* offset 0x70 */
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unsigned int resv10[2];
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unsigned int clkdcoldodpllper; /* offset 0x7c */
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unsigned int divm4dpllcore; /* offset 0x80 */
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unsigned int divm5dpllcore; /* offset 0x84 */
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unsigned int clkmoddpllmpu; /* offset 0x88 */
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unsigned int clkmoddpllper; /* offset 0x8c */
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unsigned int clkmoddpllcore; /* offset 0x90 */
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unsigned int clkmoddpllddr; /* offset 0x94 */
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unsigned int clkmoddplldisp; /* offset 0x98 */
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unsigned int clkseldpllper; /* offset 0x9c */
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unsigned int divm2dpllddr; /* offset 0xA0 */
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unsigned int divm2dplldisp; /* offset 0xA4 */
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unsigned int divm2dpllmpu; /* offset 0xA8 */
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unsigned int divm2dpllper; /* offset 0xAC */
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unsigned int resv11[1];
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unsigned int wkup_uart0ctrl; /* offset 0xB4 */
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unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
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unsigned int wkup_adctscctrl; /* offset 0xBC */
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unsigned int resv12;
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unsigned int timer1clkctrl; /* offset 0xC4 */
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unsigned int resv13[4];
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unsigned int divm6dpllcore; /* offset 0xD8 */
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};
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/**
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* Encapsulating peripheral functional clocks
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* pll registers
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*/
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struct cm_perpll {
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unsigned int l4lsclkstctrl; /* offset 0x00 */
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unsigned int l3sclkstctrl; /* offset 0x04 */
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unsigned int l4fwclkstctrl; /* offset 0x08 */
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unsigned int l3clkstctrl; /* offset 0x0c */
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unsigned int resv1;
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unsigned int cpgmac0clkctrl; /* offset 0x14 */
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unsigned int lcdclkctrl; /* offset 0x18 */
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unsigned int usb0clkctrl; /* offset 0x1C */
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unsigned int resv2;
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unsigned int tptc0clkctrl; /* offset 0x24 */
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unsigned int emifclkctrl; /* offset 0x28 */
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unsigned int ocmcramclkctrl; /* offset 0x2c */
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unsigned int gpmcclkctrl; /* offset 0x30 */
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unsigned int mcasp0clkctrl; /* offset 0x34 */
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unsigned int uart5clkctrl; /* offset 0x38 */
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unsigned int mmc0clkctrl; /* offset 0x3C */
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unsigned int elmclkctrl; /* offset 0x40 */
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unsigned int i2c2clkctrl; /* offset 0x44 */
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unsigned int i2c1clkctrl; /* offset 0x48 */
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unsigned int spi0clkctrl; /* offset 0x4C */
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unsigned int spi1clkctrl; /* offset 0x50 */
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unsigned int resv3[3];
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unsigned int l4lsclkctrl; /* offset 0x60 */
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unsigned int l4fwclkctrl; /* offset 0x64 */
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unsigned int mcasp1clkctrl; /* offset 0x68 */
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unsigned int uart1clkctrl; /* offset 0x6C */
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unsigned int uart2clkctrl; /* offset 0x70 */
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unsigned int uart3clkctrl; /* offset 0x74 */
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unsigned int uart4clkctrl; /* offset 0x78 */
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unsigned int timer7clkctrl; /* offset 0x7C */
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unsigned int timer2clkctrl; /* offset 0x80 */
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unsigned int timer3clkctrl; /* offset 0x84 */
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unsigned int timer4clkctrl; /* offset 0x88 */
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unsigned int resv4[8];
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unsigned int gpio1clkctrl; /* offset 0xAC */
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unsigned int gpio2clkctrl; /* offset 0xB0 */
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unsigned int gpio3clkctrl; /* offset 0xB4 */
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unsigned int resv5;
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unsigned int tpccclkctrl; /* offset 0xBC */
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unsigned int dcan0clkctrl; /* offset 0xC0 */
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unsigned int dcan1clkctrl; /* offset 0xC4 */
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unsigned int resv6;
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unsigned int epwmss1clkctrl; /* offset 0xCC */
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unsigned int emiffwclkctrl; /* offset 0xD0 */
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unsigned int epwmss0clkctrl; /* offset 0xD4 */
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unsigned int epwmss2clkctrl; /* offset 0xD8 */
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unsigned int l3instrclkctrl; /* offset 0xDC */
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unsigned int l3clkctrl; /* Offset 0xE0 */
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unsigned int resv8[2];
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unsigned int timer5clkctrl; /* offset 0xEC */
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unsigned int timer6clkctrl; /* offset 0xF0 */
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unsigned int mmc1clkctrl; /* offset 0xF4 */
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unsigned int mmc2clkctrl; /* offset 0xF8 */
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unsigned int resv9[8];
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unsigned int l4hsclkstctrl; /* offset 0x11C */
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unsigned int l4hsclkctrl; /* offset 0x120 */
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unsigned int resv10[8];
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unsigned int cpswclkstctrl; /* offset 0x144 */
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unsigned int lcdcclkstctrl; /* offset 0x148 */
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};
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/* Encapsulating Display pll registers */
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struct cm_dpll {
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unsigned int resv1;
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unsigned int clktimer7clk; /* offset 0x04 */
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unsigned int clktimer2clk; /* offset 0x08 */
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unsigned int clktimer3clk; /* offset 0x0C */
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unsigned int clktimer4clk; /* offset 0x10 */
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unsigned int resv2;
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unsigned int clktimer5clk; /* offset 0x18 */
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unsigned int clktimer6clk; /* offset 0x1C */
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unsigned int resv3[2];
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unsigned int clktimer1clk; /* offset 0x28 */
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unsigned int resv4[2];
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unsigned int clklcdcpixelclk; /* offset 0x34 */
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};
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struct prm_device_inst {
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unsigned int prm_rstctrl;
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unsigned int prm_rsttime;
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unsigned int prm_rstst;
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};
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#else
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/* Encapsulating core pll registers */
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struct cm_wkuppll {
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unsigned int resv0[136];
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unsigned int wkl4wkclkctrl; /* offset 0x220 */
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unsigned int resv1[7];
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unsigned int usbphy0clkctrl; /* offset 0x240 */
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unsigned int resv112;
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unsigned int usbphy1clkctrl; /* offset 0x248 */
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unsigned int resv113[45];
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unsigned int wkclkstctrl; /* offset 0x300 */
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unsigned int resv2[15];
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unsigned int wkup_i2c0ctrl; /* offset 0x340 */
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unsigned int resv3;
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unsigned int wkup_uart0ctrl; /* offset 0x348 */
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unsigned int resv4[5];
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unsigned int wkctrlclkctrl; /* offset 0x360 */
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unsigned int resv5;
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unsigned int wkgpio0clkctrl; /* offset 0x368 */
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unsigned int resv6[109];
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unsigned int clkmoddpllcore; /* offset 0x520 */
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unsigned int idlestdpllcore; /* offset 0x524 */
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unsigned int resv61;
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unsigned int clkseldpllcore; /* offset 0x52C */
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unsigned int resv7[2];
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unsigned int divm4dpllcore; /* offset 0x538 */
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unsigned int divm5dpllcore; /* offset 0x53C */
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unsigned int divm6dpllcore; /* offset 0x540 */
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unsigned int resv8[7];
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unsigned int clkmoddpllmpu; /* offset 0x560 */
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unsigned int idlestdpllmpu; /* offset 0x564 */
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unsigned int resv9;
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unsigned int clkseldpllmpu; /* offset 0x56c */
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unsigned int divm2dpllmpu; /* offset 0x570 */
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unsigned int resv10[11];
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unsigned int clkmoddpllddr; /* offset 0x5A0 */
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unsigned int idlestdpllddr; /* offset 0x5A4 */
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unsigned int resv11;
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unsigned int clkseldpllddr; /* offset 0x5AC */
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unsigned int divm2dpllddr; /* offset 0x5B0 */
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unsigned int resv12[11];
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unsigned int clkmoddpllper; /* offset 0x5E0 */
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unsigned int idlestdpllper; /* offset 0x5E4 */
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unsigned int resv13;
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unsigned int clkseldpllper; /* offset 0x5EC */
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unsigned int divm2dpllper; /* offset 0x5F0 */
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unsigned int resv14[8];
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unsigned int clkdcoldodpllper; /* offset 0x614 */
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unsigned int resv15[2];
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unsigned int clkmoddplldisp; /* offset 0x620 */
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unsigned int resv16[2];
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unsigned int clkseldplldisp; /* offset 0x62C */
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unsigned int divm2dplldisp; /* offset 0x630 */
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};
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/*
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* Encapsulating peripheral functional clocks
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* pll registers
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*/
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struct cm_perpll {
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unsigned int l3clkstctrl; /* offset 0x00 */
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unsigned int resv0[7];
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unsigned int l3clkctrl; /* Offset 0x20 */
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unsigned int resv112[7];
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unsigned int l3instrclkctrl; /* offset 0x40 */
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unsigned int resv2[3];
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unsigned int ocmcramclkctrl; /* offset 0x50 */
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unsigned int resv3[9];
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unsigned int tpccclkctrl; /* offset 0x78 */
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unsigned int resv4;
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unsigned int tptc0clkctrl; /* offset 0x80 */
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unsigned int resv5[7];
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unsigned int l4hsclkctrl; /* offset 0x0A0 */
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unsigned int resv6;
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unsigned int l4fwclkctrl; /* offset 0x0A8 */
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unsigned int resv7[85];
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unsigned int l3sclkstctrl; /* offset 0x200 */
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unsigned int resv8[7];
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unsigned int gpmcclkctrl; /* offset 0x220 */
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unsigned int resv9[5];
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unsigned int mcasp0clkctrl; /* offset 0x238 */
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unsigned int resv10;
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unsigned int mcasp1clkctrl; /* offset 0x240 */
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unsigned int resv11;
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unsigned int mmc2clkctrl; /* offset 0x248 */
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unsigned int resv12[3];
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unsigned int qspiclkctrl; /* offset 0x258 */
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unsigned int resv121;
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unsigned int usb0clkctrl; /* offset 0x260 */
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unsigned int resv122;
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unsigned int usb1clkctrl; /* offset 0x268 */
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unsigned int resv13[101];
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unsigned int l4lsclkstctrl; /* offset 0x400 */
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unsigned int resv14[7];
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unsigned int l4lsclkctrl; /* offset 0x420 */
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unsigned int resv15;
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unsigned int dcan0clkctrl; /* offset 0x428 */
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unsigned int resv16;
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unsigned int dcan1clkctrl; /* offset 0x430 */
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unsigned int resv17[13];
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unsigned int elmclkctrl; /* offset 0x468 */
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unsigned int resv18[3];
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unsigned int gpio1clkctrl; /* offset 0x478 */
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unsigned int resv19;
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unsigned int gpio2clkctrl; /* offset 0x480 */
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unsigned int resv20;
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unsigned int gpio3clkctrl; /* offset 0x488 */
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unsigned int resv41;
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unsigned int gpio4clkctrl; /* offset 0x490 */
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unsigned int resv42;
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unsigned int gpio5clkctrl; /* offset 0x498 */
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unsigned int resv21[3];
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unsigned int i2c1clkctrl; /* offset 0x4A8 */
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unsigned int resv22;
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unsigned int i2c2clkctrl; /* offset 0x4B0 */
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unsigned int resv23[3];
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unsigned int mmc0clkctrl; /* offset 0x4C0 */
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unsigned int resv24;
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unsigned int mmc1clkctrl; /* offset 0x4C8 */
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unsigned int resv25[13];
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unsigned int spi0clkctrl; /* offset 0x500 */
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unsigned int resv26;
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unsigned int spi1clkctrl; /* offset 0x508 */
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unsigned int resv27[9];
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unsigned int timer2clkctrl; /* offset 0x530 */
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unsigned int resv28;
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unsigned int timer3clkctrl; /* offset 0x538 */
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unsigned int resv29;
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unsigned int timer4clkctrl; /* offset 0x540 */
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unsigned int resv30[5];
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unsigned int timer7clkctrl; /* offset 0x558 */
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unsigned int resv31[9];
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unsigned int uart1clkctrl; /* offset 0x580 */
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unsigned int resv32;
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unsigned int uart2clkctrl; /* offset 0x588 */
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unsigned int resv33;
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unsigned int uart3clkctrl; /* offset 0x590 */
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unsigned int resv34;
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unsigned int uart4clkctrl; /* offset 0x598 */
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unsigned int resv35;
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unsigned int uart5clkctrl; /* offset 0x5A0 */
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unsigned int resv36[5];
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unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
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unsigned int resv361;
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unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
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unsigned int resv3611[79];
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unsigned int emifclkstctrl; /* offset 0x700 */
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unsigned int resv362[7];
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unsigned int emifclkctrl; /* offset 0x720 */
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unsigned int resv37[3];
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unsigned int emiffwclkctrl; /* offset 0x730 */
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unsigned int resv371;
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unsigned int otfaemifclkctrl; /* offset 0x738 */
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unsigned int resv38[57];
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unsigned int lcdclkctrl; /* offset 0x820 */
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unsigned int resv39[183];
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unsigned int cpswclkstctrl; /* offset 0xB00 */
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unsigned int resv40[7];
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unsigned int cpgmac0clkctrl; /* offset 0xB20 */
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};
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struct cm_device_inst {
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unsigned int cm_clkout1_ctrl;
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unsigned int cm_dll_ctrl;
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};
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struct prm_device_inst {
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unsigned int prm_rstctrl;
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unsigned int prm_rstst;
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};
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struct cm_dpll {
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unsigned int resv1;
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unsigned int clktimer2clk; /* offset 0x04 */
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unsigned int resv2[11];
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unsigned int clkselmacclk; /* offset 0x34 */
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};
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#endif /* CONFIG_AM43XX */
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/* Control Module RTC registers */
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struct cm_rtc {
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unsigned int rtcclkctrl; /* offset 0x0 */
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unsigned int clkstctrl; /* offset 0x4 */
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};
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/* Watchdog timer registers */
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struct wd_timer {
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unsigned int resv1[4];
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unsigned int wdtwdsc; /* offset 0x010 */
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unsigned int wdtwdst; /* offset 0x014 */
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unsigned int wdtwisr; /* offset 0x018 */
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unsigned int wdtwier; /* offset 0x01C */
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unsigned int wdtwwer; /* offset 0x020 */
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unsigned int wdtwclr; /* offset 0x024 */
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unsigned int wdtwcrr; /* offset 0x028 */
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unsigned int wdtwldr; /* offset 0x02C */
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unsigned int wdtwtgr; /* offset 0x030 */
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unsigned int wdtwwps; /* offset 0x034 */
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unsigned int resv2[3];
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unsigned int wdtwdly; /* offset 0x044 */
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unsigned int wdtwspr; /* offset 0x048 */
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unsigned int resv3[1];
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unsigned int wdtwqeoi; /* offset 0x050 */
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unsigned int wdtwqstar; /* offset 0x054 */
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unsigned int wdtwqsta; /* offset 0x058 */
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unsigned int wdtwqens; /* offset 0x05C */
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unsigned int wdtwqenc; /* offset 0x060 */
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unsigned int resv4[39];
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unsigned int wdt_unfr; /* offset 0x100 */
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|
};
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|
|
|
/* Timer 32 bit registers */
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|
struct gptimer {
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unsigned int tidr; /* offset 0x00 */
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|
unsigned char res1[12];
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|
unsigned int tiocp_cfg; /* offset 0x10 */
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|
unsigned char res2[12];
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|
unsigned int tier; /* offset 0x20 */
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|
unsigned int tistatr; /* offset 0x24 */
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|
unsigned int tistat; /* offset 0x28 */
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|
unsigned int tisr; /* offset 0x2c */
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|
unsigned int tcicr; /* offset 0x30 */
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|
unsigned int twer; /* offset 0x34 */
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|
unsigned int tclr; /* offset 0x38 */
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|
unsigned int tcrr; /* offset 0x3c */
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|
unsigned int tldr; /* offset 0x40 */
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|
unsigned int ttgr; /* offset 0x44 */
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|
unsigned int twpc; /* offset 0x48 */
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|
unsigned int tmar; /* offset 0x4c */
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|
unsigned int tcar1; /* offset 0x50 */
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|
unsigned int tscir; /* offset 0x54 */
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|
unsigned int tcar2; /* offset 0x58 */
|
|
};
|
|
|
|
/* UART Registers */
|
|
struct uart_sys {
|
|
unsigned int resv1[21];
|
|
unsigned int uartsyscfg; /* offset 0x54 */
|
|
unsigned int uartsyssts; /* offset 0x58 */
|
|
};
|
|
|
|
/* VTP Registers */
|
|
struct vtp_reg {
|
|
unsigned int vtp0ctrlreg;
|
|
};
|
|
|
|
/* Control Status Register */
|
|
struct ctrl_stat {
|
|
unsigned int resv1[16];
|
|
unsigned int statusreg; /* ofset 0x40 */
|
|
unsigned int resv2[51];
|
|
unsigned int secure_emif_sdram_config; /* offset 0x0110 */
|
|
unsigned int resv3[319];
|
|
unsigned int dev_attr;
|
|
};
|
|
|
|
/* AM33XX GPIO registers */
|
|
#define OMAP_GPIO_REVISION 0x0000
|
|
#define OMAP_GPIO_SYSCONFIG 0x0010
|
|
#define OMAP_GPIO_SYSSTATUS 0x0114
|
|
#define OMAP_GPIO_IRQSTATUS1 0x002c
|
|
#define OMAP_GPIO_IRQSTATUS2 0x0030
|
|
#define OMAP_GPIO_CTRL 0x0130
|
|
#define OMAP_GPIO_OE 0x0134
|
|
#define OMAP_GPIO_DATAIN 0x0138
|
|
#define OMAP_GPIO_DATAOUT 0x013c
|
|
#define OMAP_GPIO_LEVELDETECT0 0x0140
|
|
#define OMAP_GPIO_LEVELDETECT1 0x0144
|
|
#define OMAP_GPIO_RISINGDETECT 0x0148
|
|
#define OMAP_GPIO_FALLINGDETECT 0x014c
|
|
#define OMAP_GPIO_DEBOUNCE_EN 0x0150
|
|
#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
|
|
#define OMAP_GPIO_CLEARDATAOUT 0x0190
|
|
#define OMAP_GPIO_SETDATAOUT 0x0194
|
|
|
|
/* Control Device Register */
|
|
|
|
/* Control Device Register */
|
|
#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
|
|
#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
|
|
#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
|
|
|
|
struct ctrl_dev {
|
|
unsigned int deviceid; /* offset 0x00 */
|
|
unsigned int resv1[7];
|
|
unsigned int usb_ctrl0; /* offset 0x20 */
|
|
unsigned int resv2;
|
|
unsigned int usb_ctrl1; /* offset 0x28 */
|
|
unsigned int resv3;
|
|
unsigned int macid0l; /* offset 0x30 */
|
|
unsigned int macid0h; /* offset 0x34 */
|
|
unsigned int macid1l; /* offset 0x38 */
|
|
unsigned int macid1h; /* offset 0x3c */
|
|
unsigned int resv4[4];
|
|
unsigned int miisel; /* offset 0x50 */
|
|
unsigned int resv5[4];
|
|
unsigned int pwmssctrl; /* offset 0x64 */
|
|
unsigned int resv6[2];
|
|
unsigned int mreqprio_0; /* offset 0x70 */
|
|
unsigned int mreqprio_1; /* offset 0x74 */
|
|
unsigned int resv7[97];
|
|
unsigned int efuse_sma; /* offset 0x1FC */
|
|
};
|
|
|
|
/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
|
|
#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
|
|
#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
|
|
#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
|
|
|
|
struct l3f_cfg_bwlimiter {
|
|
u32 padding0[2];
|
|
u32 modena_init0_bw_fractional;
|
|
u32 modena_init0_bw_integer;
|
|
u32 modena_init0_watermark_0;
|
|
};
|
|
|
|
/* gmii_sel register defines */
|
|
#define GMII1_SEL_MII 0x0
|
|
#define GMII1_SEL_RMII 0x1
|
|
#define GMII1_SEL_RGMII 0x2
|
|
#define GMII2_SEL_MII 0x0
|
|
#define GMII2_SEL_RMII 0x4
|
|
#define GMII2_SEL_RGMII 0x8
|
|
#define RGMII1_IDMODE BIT(4)
|
|
#define RGMII2_IDMODE BIT(5)
|
|
#define RMII1_IO_CLK_EN BIT(6)
|
|
#define RMII2_IO_CLK_EN BIT(7)
|
|
|
|
#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
|
|
#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
|
|
#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
|
|
#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
|
|
#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
|
|
|
|
/* PWMSS */
|
|
struct pwmss_regs {
|
|
unsigned int idver;
|
|
unsigned int sysconfig;
|
|
unsigned int clkconfig;
|
|
unsigned int clkstatus;
|
|
};
|
|
#define ECAP_CLK_EN BIT(0)
|
|
#define ECAP_CLK_STOP_REQ BIT(1)
|
|
|
|
struct pwmss_ecap_regs {
|
|
unsigned int tsctr;
|
|
unsigned int ctrphs;
|
|
unsigned int cap1;
|
|
unsigned int cap2;
|
|
unsigned int cap3;
|
|
unsigned int cap4;
|
|
unsigned int resv1[4];
|
|
unsigned short ecctl1;
|
|
unsigned short ecctl2;
|
|
};
|
|
|
|
/* Capture Control register 2 */
|
|
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
|
|
#define ECTRL2_MDSL_ECAP BIT(9)
|
|
#define ECTRL2_CTRSTP_FREERUN BIT(4)
|
|
#define ECTRL2_PLSL_LOW BIT(10)
|
|
#define ECTRL2_SYNC_EN BIT(5)
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __KERNEL_STRICT_NAMES */
|
|
|
|
#endif /* _AM33XX_CPU_H */
|