103 lines
4.4 KiB
C
103 lines
4.4 KiB
C
/*
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* DMA Masks
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*/
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#ifndef __BFIN_PERIPHERAL_DMA__
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#define __BFIN_PERIPHERAL_DMA__
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/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
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#define DMAEN 0x0001 /* DMA Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#ifdef CONFIG_BF60x
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#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
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#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
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#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
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#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
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#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
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#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
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#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
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#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
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#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
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#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
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#define DI_EN_X 0x00100000 /* Data Int Enable in X count */
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#define DI_EN_Y 0x00200000 /* Data Int Enable in Y count */
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#define DI_EN_P 0x00300000 /* Data Int Enable in Peri */
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#define DI_EN DI_EN_X /* Data Int Enable */
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#define NDSIZE_0 0x00000000 /* Next Desc Size = 0 */
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#define NDSIZE_1 0x00010000 /* Next Desc Size = 1 */
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#define NDSIZE_2 0x00020000 /* Next Desc Size = 2 */
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#define NDSIZE_3 0x00030000 /* Next Desc Size = 3 */
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#define NDSIZE_4 0x00040000 /* Next Desc Size = 4 */
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#define NDSIZE_5 0x00050000 /* Next Desc Size = 5 */
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#define NDSIZE_6 0x00060000 /* Next Desc Size = 6 */
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#define NDSIZE 0x00070000 /* Next Desc Size */
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#define NDSIZE_OFFSET 16 /* Next Desc Size Offset */
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#define DMAFLOW_LIST 0x00004000 /* Desc List Mode */
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#define DMAFLOW_ARRAY 0x00005000 /* Desc Array Mode */
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#define DMAFLOW_LIST_DEMAND 0x00006000 /* Desc Demand List Mode */
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#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Desc Demand Array Mode */
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#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Run (DFETCH) */
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#define DMA_RUN 0x00000200 /* DMA Channel Run */
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#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Run (WAIT TRIG)*/
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#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Run (WAIT ACK) */
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#else
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define PSIZE_16 WDSIZE_16
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#define PSIZE_32 WDSIZE_32
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define NDSIZE 0x0F00 /* Next Descriptor bitmask */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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#define DMAEN_P 0 /* Channel Enable */
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#define WNR_P 1 /* Channel Direction (W/R*) */
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#define WDSIZE_P 2 /* Transfer Word Size */
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#define DMA2D_P 4 /* 2D/1D* Mode */
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#define RESTART_P 5 /* Restart */
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#define DI_SEL_P 6 /* Data Interrupt Select */
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#define DI_EN_P 7 /* Data Interrupt Enable */
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/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
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#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
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#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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#endif
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#define DMAFLOW 0x7000 /* Flow Control */
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#define FLOW_STOP 0x0000 /* Stop Mode */
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#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMA_DONE_P 0 /* DMA Done Indicator */
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#define DMA_ERR_P 1 /* DMA Error Indicator */
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#define DFETCH_P 2 /* Descriptor Fetch Indicator */
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#define DMA_RUN_P 3 /* DMA Running Indicator */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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#define CTYPE 0x0040 /* DMA Channel Type (Mem/Peri) */
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#define CTYPE_P 6 /* DMA Channel Type BIT POSITION */
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#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
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#endif
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