184 lines
3.9 KiB
C
184 lines
3.9 KiB
C
/*
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* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <netdev.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MODEMR (0xFFCC0020)
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#define MODEMR_MASK (0x6)
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#define MODEMR_533MHZ (0x2)
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int checkboard(void)
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{
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u32 r = readl(MODEMR);
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if ((r & MODEMR_MASK) & MODEMR_533MHZ)
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puts("CPU Clock: 533MHz\n");
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else
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puts("CPU Clock: 400MHz\n");
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puts("BOARD: Alpha Project. AP-SH4A-4A\n");
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return 0;
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}
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#define MSTPSR1 (0xFFC80044)
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#define MSTPCR1 (0xFFC80034)
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#define MSTPSR1_GETHER (1 << 14)
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/* IPSR3 */
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#define ET0_ETXD0 (0x4 << 3)
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#define ET0_GTX_CLK_A (0x4 << 6)
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#define ET0_ETXD1_A (0x4 << 9)
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#define ET0_ETXD2_A (0x4 << 12)
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#define ET0_ETXD3_A (0x4 << 15)
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#define ET0_ETXD4 (0x3 << 18)
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#define ET0_ETXD5_A (0x5 << 21)
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#define ET0_ETXD6_A (0x5 << 24)
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#define ET0_ETXD7 (0x4 << 27)
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#define IPSR3_ETH_ENABLE \
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(ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
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ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
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/* IPSR4 */
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#define ET0_ERXD7 (0x4)
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#define ET0_RX_DV (0x4 << 3)
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#define ET0_RX_ER (0x4 << 6)
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#define ET0_CRS (0x4 << 9)
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#define ET0_COL (0x4 << 12)
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#define ET0_MDC (0x4 << 15)
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#define ET0_MDIO_A (0x3 << 18)
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#define ET0_LINK_A (0x3 << 20)
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#define ET0_PHY_INT_A (0x3 << 24)
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#define IPSR4_ETH_ENABLE \
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(ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
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ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
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/* IPSR8 */
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#define ET0_ERXD0 (0x4 << 20)
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#define ET0_ERXD1 (0x4 << 23)
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#define ET0_ERXD2_A (0x3 << 26)
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#define ET0_ERXD3_A (0x3 << 28)
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#define IPSR8_ETH_ENABLE \
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(ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
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/* IPSR10 */
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#define RX4_D (0x1 << 22)
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#define TX4_D (0x1 << 23)
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#define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
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/* IPSR11 */
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#define ET0_ERXD4 (0x4 << 4)
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#define ET0_ERXD5 (0x4 << 7)
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#define ET0_ERXD6 (0x3 << 10)
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#define ET0_TX_EN (0x2 << 19)
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#define ET0_TX_ER (0x2 << 21)
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#define ET0_TX_CLK_A (0x4 << 23)
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#define ET0_RX_CLK_A (0x3 << 26)
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#define IPSR11_ETH_ENABLE \
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(ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
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ET0_TX_CLK_A | ET0_RX_CLK_A)
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#define GPSR1_INIT (0xFFFF7FFF)
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#define GPSR2_INIT (0x4005FEFF)
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#define GPSR3_INIT (0x2EFFFFFF)
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#define GPSR4_INIT (0xC7000000)
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int board_init(void)
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{
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u32 data;
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/* Set IPSR register */
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data = readl(IPSR3);
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data |= IPSR3_ETH_ENABLE;
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writel(~data, PMMR);
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writel(data, IPSR3);
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data = readl(IPSR4);
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data |= IPSR4_ETH_ENABLE;
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writel(~data, PMMR);
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writel(data, IPSR4);
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data = readl(IPSR8);
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data |= IPSR8_ETH_ENABLE;
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writel(~data, PMMR);
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writel(data, IPSR8);
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data = readl(IPSR10);
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data |= IPSR10_SCIF_ENABLE;
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writel(~data, PMMR);
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writel(data, IPSR10);
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data = readl(IPSR11);
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data |= IPSR11_ETH_ENABLE;
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writel(~data, PMMR);
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writel(data, IPSR11);
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/* GPIO select */
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data = GPSR1_INIT;
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writel(~data, PMMR);
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writel(data, GPSR1);
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data = GPSR2_INIT;
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writel(~data, PMMR);
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writel(data, GPSR2);
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data = GPSR3_INIT;
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writel(~data, PMMR);
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writel(data, GPSR3);
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data = GPSR4_INIT;
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writel(~data, PMMR);
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writel(data, GPSR4);
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data = 0x0;
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writel(~data, PMMR);
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writel(data, GPSR5);
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/* mode select */
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data = MODESEL2_INIT;
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writel(~data, PMMR);
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writel(data, MODESEL2);
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#if defined(CONFIG_SH_ETHER)
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u32 r = readl(MSTPSR1);
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if (r & MSTPSR1_GETHER)
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writel((r & ~MSTPSR1_GETHER), MSTPCR1);
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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u8 mac[6];
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/* Read Mac Address and set*/
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
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/* Read MAC address */
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i2c_read(0x50, 0x0, 0, mac, 6);
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if (is_valid_ethaddr(mac))
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eth_setenv_enetaddr("ethaddr", mac);
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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