512 lines
12 KiB
Plaintext
512 lines
12 KiB
Plaintext
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "fsl-imx8mq.dtsi"
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/ {
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model = "Freescale i.MX8MQ DDR4 ARM2";
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compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
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bcmdhd_wlan_0: bcmdhd_wlan@0 {
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compatible = "android,bcmdhd_wlan";
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bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin";
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bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal";
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};
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chosen {
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bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
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stdout-path = &uart1;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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modem_reset: modem-reset {
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compatible = "gpio-reset";
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reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
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reset-delay-us = <2000>;
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reset-post-delay-ms = <40>;
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#reset-cells = <0>;
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};
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wm8524: wm8524 {
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compatible = "wlf,wm8524";
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clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
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clock-names = "mclk";
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wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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};
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sound-wm8524 {
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compatible = "fsl,imx-audio-wm8524";
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model = "wm8524-audio";
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audio-cpu = <&sai2>;
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audio-codec = <&wm8524>;
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audio-routing =
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"Line Out Jack", "LINEVOUTL",
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"Line Out Jack", "LINEVOUTR";
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};
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pwmleds {
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compatible = "pwm-leds";
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ledpwm2 {
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label = "PWM2";
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pwms = <&pwm2 0 50000>;
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max-brightness = <255>;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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imx8mq-arm2 {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
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>;
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};
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pinctrl_i2c1_gpio: i2c1grp-gpio {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f
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MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f
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>;
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};
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pinctrl_i2c2_gpio: i2c2grp-gpio {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f
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MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16
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MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
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MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
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>;
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};
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pinctrl_pcie1: pcie1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16
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MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
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MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
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>;
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};
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pinctrl_pwm2: pwm2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
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MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
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MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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at803x,led-act-blind-workaround;
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at803x,eee-disabled;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pmic: pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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&pcie0{
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>;
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disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>;
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reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie1{
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie1>;
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clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
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disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>;
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reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "okay";
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};
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&uart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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status = "okay";
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};
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&lcdif {
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status = "okay";
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disp-dev = "mipi_dsi_northwest";
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display = <&display0>;
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display0: display@0 {
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bits-per-pixel = <24>;
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bus-width = <24>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <9200000>;
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hactive = <480>;
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vactive = <272>;
|
|
hfront-porch = <8>;
|
|
hback-porch = <4>;
|
|
hsync-len = <41>;
|
|
vback-porch = <2>;
|
|
vfront-porch = <4>;
|
|
vsync-len = <10>;
|
|
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
|
bus-width = <4>;
|
|
cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_phy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_dwc3_0 {
|
|
status = "okay";
|
|
dr_mode = "peripheral";
|
|
};
|
|
|
|
&usb3_phy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_dwc3_1 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|