421 lines
10 KiB
Plaintext
421 lines
10 KiB
Plaintext
/*
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x80000000 0x00020000;
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#include "fsl-imx8qm.dtsi"
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/ {
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model = "Freescale i.MX8QM ARM2";
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compatible = "fsl,imx8qm-arm2", "fsl,imx8qm";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
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stdout-path = &lpuart0;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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user {
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label = "heartbeat";
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gpios = <&gpio2 15 0>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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imx8qm-arm2 {
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048
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SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048
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SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048
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SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048
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SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048
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SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048
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SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048
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SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048
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SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048
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SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048
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SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048
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SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048
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>;
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};
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pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
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fsl,pins = <
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SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
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SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
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>;
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};
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pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
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fsl,pins = <
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SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
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SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc3_gpio: usdhc3grpgpio {
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fsl,pins = <
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SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
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/* WP */
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SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
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/* CD */
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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/* WP */
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SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020
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/* CD */
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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/* WP */
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SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020
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/* CD */
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020
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SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020
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/*
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* Change the default alt function from SCL/SDA to others,
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* to avoid select input conflict with GPT0
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*/
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SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c
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SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c
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SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c
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SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c
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>;
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};
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pinctrl_lpspi0: lpspi0grp {
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fsl,pins = <
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SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c
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SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c
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SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c
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SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c
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SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c
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>;
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};
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pinctrl_flexspi0: flexspi0grp {
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fsl,pins = <
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SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
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SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
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SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
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SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
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SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
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SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
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SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
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SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
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SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
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SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
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SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
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SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
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SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
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SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
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SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
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SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
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>;
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};
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pinctrl_gpio_leds: gpioledsgrp {
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fsl,pins = <
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SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
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>;
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};
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};
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};
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&gpio2 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
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no-1-8-v;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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srp-disable;
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hnp-disable;
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adp-disable;
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disable-over-current;
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec2>;
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phy-mode = "rgmii";
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phy-handle = <ðphy1>;
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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status = "okay";
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};
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&flexspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi0>;
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status = "okay";
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flash0: mt35xu512aba@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <8>;
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};
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};
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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status = "okay";
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pca9557_a: gpio@18 {
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compatible = "nxp,pca9557";
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reg = <0x18>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_b: gpio@19 {
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compatible = "nxp,pca9557";
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reg = <0x19>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_c: gpio@1b {
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compatible = "nxp,pca9557";
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reg = <0x1b>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_d: gpio@1f {
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compatible = "nxp,pca9557";
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reg = <0x1f>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c1_lvds0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
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clock-frequency = <100000>;
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status = "okay";
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it6263-0@4c {
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compatible = "ITE,it6263";
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reg = <0x4c>;
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};
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};
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&i2c1_lvds1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
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clock-frequency = <100000>;
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status = "okay";
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it6263-1@4c {
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compatible = "ITE,it6263";
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reg = <0x4c>;
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};
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};
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&lpspi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi0>;
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status = "okay";
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spidev0: spi@0 {
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reg = <0>;
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compatible = "rohm,dh2228fv";
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spi-max-frequency = <4000000>;
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};
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};
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&lpuart1 {
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status = "okay";
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};
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