48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __ASM_ARCH_IMX8_I2C_H__
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#define __ASM_ARCH_IMX8_I2C_H__
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#include <asm/mach-imx/sci/sci.h>
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#include <asm/arch/lpcg.h>
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struct imx_i2c_map {
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unsigned index;
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sc_rsrc_t rsrc;
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u32 lpcg[4];
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};
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static struct imx_i2c_map imx_i2c_desc[] = {
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{0, SC_R_I2C_0, {LPI2C_0_LPCG}},
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{1, SC_R_I2C_1, {LPI2C_1_LPCG}},
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{2, SC_R_I2C_2, {LPI2C_2_LPCG}},
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{3, SC_R_I2C_3, {LPI2C_3_LPCG}},
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#ifdef CONFIG_IMX8QM
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{4, SC_R_I2C_4, {LPI2C_4_LPCG}},
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#endif
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{5, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c0 */
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{6, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c1 */
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{7, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c0 */
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{8, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c1 */
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{9, SC_R_CSI_0_I2C_0, {MIPI_CSI_0_LPCG + 0x14}},
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{10, SC_R_CSI_1_I2C_0, {MIPI_CSI_1_LPCG + 0x14}},
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{11, SC_R_HDMI_I2C_0, {DI_HDMI_LPCG}},
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{12, SC_R_HDMI_RX_I2C_0, {RX_HDMI_LPCG + 0x10, RX_HDMI_LPCG + 0x14, RX_HDMI_LPCG + 0x18, RX_HDMI_LPCG + 0x1C}},
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#ifdef CONFIG_IMX8QM
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{13, SC_R_MIPI_0_I2C_0, {MIPI_DSI_0_LPCG + 0x14, MIPI_DSI_0_LPCG + 0x18, MIPI_DSI_0_LPCG + 0x1c}},
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{14, SC_R_MIPI_0_I2C_1, {MIPI_DSI_0_LPCG + 0x24, MIPI_DSI_0_LPCG + 0x28, MIPI_DSI_0_LPCG + 0x2c}},
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{15, SC_R_MIPI_1_I2C_0, {MIPI_DSI_1_LPCG + 0x14, MIPI_DSI_1_LPCG + 0x18, MIPI_DSI_1_LPCG + 0x1c}},
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{16, SC_R_MIPI_1_I2C_1, {MIPI_DSI_1_LPCG + 0x24, MIPI_DSI_1_LPCG + 0x28, MIPI_DSI_1_LPCG + 0x2c}},
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#else
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{13, SC_R_MIPI_0_I2C_0, {DI_MIPI0_LPCG + 0x10}},
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{14, SC_R_MIPI_0_I2C_1, {DI_MIPI0_LPCG + 0x14}},
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{15, SC_R_MIPI_1_I2C_0, {DI_MIPI1_LPCG + 0x10}},
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{16, SC_R_MIPI_1_I2C_1, {DI_MIPI1_LPCG + 0x14}},
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#endif
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};
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#endif /* __ASM_ARCH_IMX8_I2C_H__ */
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