116 lines
4.1 KiB
C
116 lines
4.1 KiB
C
/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _IMX8_LVDS_H_
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#define _IMX8_LVDS_H_
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#define IMX_LVDS_SET_FIELD(__field__, __value__) (((__value__) << (__field__ ## _SHIFT)) & (__field__ ## _MASK))
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#define IMX_LVDS_GET_FIELD(__field__, __reg__) (((__reg__) & (__field__ ## _MASK)) >> (__field__ ## _SHIFT))
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#define IMX_LVDS_SET(__reg__) (reg+0x4)
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#define IMX_LVDS_CLEAR(__reg__) (reg+0x8)
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#define IMX_LVDS_TOGGLE(__reg__)(reg+0x4)
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#define LVDS_CTRL 0x0e0
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#define LVDS_CTRL_CH0_MODE_MASK 0x03U
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#define LVDS_CTRL_CH0_MODE_SHIFT 0U
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#define LVDS_CTRL_CH0_MODE__DISABLED 0x00U
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#define LVDS_CTRL_CH0_MODE__DI0 0x01U
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#define LVDS_CTRL_CH0_MODE__RESERVED 0x02U
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#define LVDS_CTRL_CH0_MODE__DI1 0x03U
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#define LVDS_CTRL_CH1_MODE_MASK 0x0cU
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#define LVDS_CTRL_CH1_MODE_SHIFT 2U
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#define LVDS_CTRL_CH1_MODE__DISABLED 0x00U
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#define LVDS_CTRL_CH1_MODE__DI0 0x01U
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#define LVDS_CTRL_CH1_MODE__RESERVED 0x02U
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#define LVDS_CTRL_CH1_MODE__DI1 0x03U
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#define LVDS_CTRL_SPLIT_MODE_MASK 0x10U
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#define LVDS_CTRL_SPLIT_MODE_SHIFT 4U
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#define LVDS_CTRL_SPLIT_MODE__DISABLE 0x00U
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#define LVDS_CTRL_SPLIT_MODE__ENABLE 0x01U
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#define LVDS_CTRL_CH0_DATA_WIDTH_MASK 0x20U
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#define LVDS_CTRL_CH0_DATA_WIDTH_SHIFT 5U
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#define LVDS_CTRL_CH0_DATA_WIDTH__18BIT 0x00U
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#define LVDS_CTRL_CH0_DATA_WIDTH__24BIT 0x01U
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#define LVDS_CTRL_CH0_BIT_MAP_MASK 0x40U
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#define LVDS_CTRL_CH0_BIT_MAP_SHIFT 6U
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#define LVDS_CTRL_CH0_BIT_MAP__SWWG 0x00U
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#define LVDS_CTRL_CH0_BIT_MAP__JEIDA 0x01U
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#define LVDS_CTRL_CH1_DATA_WIDTH_MASK 0x80U
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#define LVDS_CTRL_CH1_DATA_WIDTH_SHIFT 7U
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#define LVDS_CTRL_CH1_DATA_WIDTH__18BIT 0x00U
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#define LVDS_CTRL_CH1_DATA_WIDTH__24BIT 0x01U
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#define LVDS_CTRL_CH1_BIT_MAP_MASK 0x100U
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#define LVDS_CTRL_CH1_BIT_MAP_SHIFT 8U
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#define LVDS_CTRL_CH1_BIT_MAP__SWWG 0x00U
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#define LVDS_CTRL_CH1_BIT_MAP__JEIDA 0x01U
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#define LVDS_CTRL_DI0_VSYNC_POL_MASK 0x200U
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#define LVDS_CTRL_DI0_VSYNC_POL_SHIFT 9U
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#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_LOW 0x00U
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#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_HIGH 0x01U
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#define LVDS_CTRL_DI1_VSYNC_POL_MASK 0x400U
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#define LVDS_CTRL_DI1_VSYNC_POL_SHIFT 10U
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#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_LOW 0x00U
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#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_HIGH 0x01U
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#define LVDS_CTRL_CH0_10BIT_ENABLE_MASK 0x400000U
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#define LVDS_CTRL_CH0_10BIT_ENABLE_SHIFT 22U
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#define LVDS_CTRL_CH0_10BIT_ENABLE__USE_DATA_WIDTH 0x00U
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#define LVDS_CTRL_CH0_10BIT_ENABLE__10BIT 0x01U
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#define LVDS_CTRL_CH1_10BIT_ENABLE_MASK 0x800000U
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#define LVDS_CTRL_CH1_10BIT_ENABLE_SHIFT 23U
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#define LVDS_CTRL_CH1_10BIT_ENABLE__USE_DATA_WIDTH 0x00U
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#define LVDS_CTRL_CH1_10BIT_ENABLE__10BIT 0x01U
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#define LVDS_CTRL_DI0_DATA_WIDTH_MASK 0x03000000U
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#define LVDS_CTRL_DI0_DATA_WIDTH_SHIFT 24U
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#define LVDS_CTRL_DI0_DATA_WIDTH__USE_18BIT 0x00U
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#define LVDS_CTRL_DI0_DATA_WIDTH__USE_24BIT 0x1U
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#define LVDS_CTRL_DI0_DATA_WIDTH__USE_30BIT 0x2U
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#define LVDS_CTRL_DI1_DATA_WIDTH_MASK 0x0C000000U
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#define LVDS_CTRL_DI1_DATA_WIDTH_SHIFT 26U
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#define LVDS_CTRL_DI1_DATA_WIDTH__USE_18BIT 0x00U
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#define LVDS_CTRL_DI1_DATA_WIDTH__USE_24BIT 0x1U
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#define LVDS_CTRL_DI1_DATA_WIDTH__USE_30BIT 0x2U
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#define LVDS_PHY_CTRL (0x0)
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#define LVDS_PHY_CTRL_PD_MASK (1<<0)
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#define LVDS_PHY_CTRL_PD_SHIFT (0)
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#define LVDS_PHY_CTRL_RFB_MASK (1<<1)
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#define LVDS_PHY_CTRL_RFB_SHIFT (1)
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#define LVDS_PHY_CTRL_NB_MASK (1<<2)
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#define LVDS_PHY_CTRL_NB_SHIFT (2)
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#define LVDS_PHY_CTRL_CH0_EN_MASK (1<<3)
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#define LVDS_PHY_CTRL_CH0_EN_SHIFT (3)
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#define LVDS_PHY_CTRL_CH1_EN_MASK (1<<4)
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#define LVDS_PHY_CTRL_CH1_EN_SHIFT (4)
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#define LVDS_PHY_CTRL_TST_MASK (0x3f<<5)
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#define LVDS_PHY_CTRL_TST_SHIFT (5)
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#define LVDS_PHY_CTRL_CA_MASK (0x7<<11)
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#define LVDS_PHY_CTRL_CA_SHIFT (11)
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#define LVDS_PHY_CTRL_CCM_MASK (0x7<<14)
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#define LVDS_PHY_CTRL_CCM_SHIFT (14)
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#define LVDS_PHY_CTRL_M_MASK (0x3<<17)
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#define LVDS_PHY_CTRL_M_SHIFT (17)
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#endif /* _IMX8_LVDS_H_ */
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