201 lines
6.2 KiB
C
201 lines
6.2 KiB
C
/*
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* Copyright 2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SC_LPCG_H
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#define _SC_LPCG_H
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/*LSIO SS */
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#define PWM_0_LPCG 0x5D400000
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#define PWM_1_LPCG 0x5D410000
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#define PWM_2_LPCG 0x5D420000
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#define PWM_3_LPCG 0x5D430000
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#define PWM_4_LPCG 0x5D440000
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#define PWM_5_LPCG 0x5D450000
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#define PWM_6_LPCG 0x5D460000
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#define PWM_7_LPCG 0x5D470000
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#define GPIO_0_LPCG 0x5D480000
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#define GPIO_1_LPCG 0x5D490000
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#define GPIO_2_LPCG 0x5D4A0000
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#define GPIO_3_LPCG 0x5D4B0000
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#define GPIO_4_LPCG 0x5D4C0000
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#define GPIO_5_LPCG 0x5D4D0000
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#define GPIO_6_LPCG 0x5D4E0000
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#define GPIO_7_LPCG 0x5D4F0000
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#define FSPI_0_LPCG 0x5D520000
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#define FSPI_1_LPCG 0x5D530000
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#define GPT_0_LPCG 0x5D540000
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#define GPT_1_LPCG 0x5D550000
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#define GPT_2_LPCG 0x5D560000
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#define GPT_3_LPCG 0x5D570000
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#define GPT_4_LPCG 0x5D580000
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#define OCRAM_LPCG 0x5D590000
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#define KPP_LPCG 0x5D5A0000
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#define MU_5A_LPCG 0x5D600000
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#define MU_6A_LPCG 0x5D610000
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#define MU_7A_LPCG 0x5D620000
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#define MU_8A_LPCG 0x5D630000
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#define MU_9A_LPCG 0x5D640000
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#define MU_10A_LPCG 0x5D650000
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#define MU_11A_LPCG 0x5D660000
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#define MU_12A_LPCG 0x5D670000
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#define MU_13A_LPCG 0x5D680000
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/* HSIO SS */
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#define CRR_5_LPCG 0x5F0F0000
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#define CRR_4_LPCG 0x5F0E0000
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#define CRR_3_LPCG 0x5F0D0000
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#define CRR_2_LPCG 0x5F0C0000
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#define CRR_1_LPCG 0x5F0B0000
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#define CRR_0_LPCG 0x5F0A0000
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#define PHY_1_LPCG 0x5F090000
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#define PHY_2_LPCG 0x5F080000
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#define SATA_0_LPCG 0x5F070000
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#define PCIE_B_LPCG 0x5F060000
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#define PCIE_A_LPCG 0x5F050000
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/* DMA SS */
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#define FLEX_CAN_2_LPCG 0x5ACF0000
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#define FLEX_CAN_1_LPCG 0x5ACE0000
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#define FLEX_CAN_0_LPCG 0x5ACD0000
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#define FTM_1_LPCG 0x5ACB0000
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#define FTM_0_LPCG 0x5ACA0000
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#define ADC_1_LPCG 0x5AC90000
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#define ADC_0_LPCG 0x5AC80000
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#define LPI2C_4_LPCG 0x5AC40000
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#define LPI2C_3_LPCG 0x5AC30000
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#define LPI2C_2_LPCG 0x5AC20000
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#define LPI2C_1_LPCG 0x5AC10000
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#define LPI2C_0_LPCG 0x5AC00000
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#define EMVSIM_1_LPCG 0x5A4E0000
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#define EMVSIM_0_LPCG 0x5A4D0000
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#define LPUART_4_LPCG 0x5A4A0000
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#define LPUART_3_LPCG 0x5A490000
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#define LPUART_2_LPCG 0x5A480000
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#define LPUART_1_LPCG 0x5A470000
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#define LPUART_0_LPCG 0x5A460000
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#define LPSPI_3_LPCG 0x5A430000
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#define LPSPI_2_LPCG 0x5A420000
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#define LPSPI_1_LPCG 0x5A410000
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#define LPSPI_0_LPCG 0x5A400000
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/* Display SS */
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#define DC_0_LPCG 0x56010000
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#define DC_1_LPCG 0x57010000
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/* LVDS */
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#define DI_LVDS_0_LPCG 0x56243000
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#define DI_LVDS_1_LPCG 0x57243000
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/* DI HDMI */
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#define DI_HDMI_LPCG 0x56263000
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/* RX-HDMI */
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#define RX_HDMI_LPCG 0x58263000
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/* MIPI CSI SS */
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#define MIPI_CSI_0_LPCG 0x58223000
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#define MIPI_CSI_1_LPCG 0x58243000
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/* MIPI DSI SS */
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#define MIPI_DSI_0_LPCG 0x56223000
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#define MIPI_DSI_1_LPCG 0x57223000
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/* Imaging SS */
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#define IMG_JPEG_ENC_LPCG 0x585F0000
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#define IMG_JPEG_DEC_LPCG 0x585D0000
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#define IMG_PXL_LINK_DC1_LPCG 0x585C0000
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#define IMG_PXL_LINK_DC0_LPCG 0x585B0000
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#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000
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#define IMG_PXL_LINK_CSI1_LPCG 0x58590000
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#define IMG_PXL_LINK_CSI0_LPCG 0x58580000
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#define IMG_PDMA_7_LPCG 0x58570000
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#define IMG_PDMA_6_LPCG 0x58560000
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#define IMG_PDMA_5_LPCG 0x58550000
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#define IMG_PDMA_4_LPCG 0x58540000
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#define IMG_PDMA_3_LPCG 0x58530000
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#define IMG_PDMA_2_LPCG 0x58520000
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#define IMG_PDMA_1_LPCG 0x58510000
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#define IMG_PDMA_0_LPCG 0x58500000
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/* HSIO SS */
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#define HSIO_GPIO_LPCG 0x5F100000
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#define HSIO_MISC_LPCG 0x5F0F0000
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#define HSIO_SATA_CRR4_LPCG 0x5F0E0000
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#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000
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#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000
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#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000
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#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000
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#define HSIO_PHY_X1_LPCG 0x5F090000
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#define HSIO_PHY_X2_LPCG 0x5F080000
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#define HSIO_SATA_LPCG 0x5F070000
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#define HSIO_PCIE_X1_LPCG 0x5F060000
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#define HSIO_PCIE_X2_LPCG 0x5F050000
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/* M4 SS */
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#define M4_0_I2C_LPCG 0x37630000
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#define M4_0_LPUART_LPCG 0x37620000
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#define M4_0_LPIT_LPCG 0x37610000
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#define M4_1_I2C_LPCG 0x3B630000
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#define M4_1_LPUART_LPCG 0x3B620000
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#define M4_1_LPIT_LPCG 0x3B610000
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/* Audio SS */
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#define AUD_ASRC_0_LPCG 0x59400000
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#define AUD_ESAI_0_LPCG 0x59410000
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#define AUD_SPDIF_0_LPCG 0x59420000
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#define AUD_SPDIF_1_LPCG 0x59430000
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#define AUD_SAI_0_LPCG 0x59440000
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#define AUD_SAI_1_LPCG 0x59450000
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#define AUD_SAI_2_LPCG 0x59460000
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#define AUD_SAI_3_LPCG 0x59470000
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#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000
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#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000
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#define AUD_GPT_5_LPCG 0x594B0000
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#define AUD_GPT_6_LPCG 0x594C0000
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#define AUD_GPT_7_LPCG 0x594D0000
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#define AUD_GPT_8_LPCG 0x594E0000
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#define AUD_GPT_9_LPCG 0x594F0000
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#define AUD_GPT_10_LPCG 0x59500000
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#define AUD_DSP_LPCG 0x59580000
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#define AUD_OCRAM_LPCG 0x59590000
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#define AUD_EDMA_0_LPCG 0x595f0000
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#define AUD_ASRC_1_LPCG 0x59c00000
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#define AUD_ESAI_1_LPCG 0x59c10000
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#define AUD_SAI_6_LPCG 0x59c20000
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#define AUD_SAI_7_LPCG 0x59c30000
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#define AUD_AMIX_LPCG 0x59c40000
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#define AUD_MQS_LPCG 0x59c50000
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#define AUD_ACM_LPCG 0x59c60000
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#define AUD_REC_CLK0_LPCG 0x59d00000
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#define AUD_REC_CLK1_LPCG 0x59d10000
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#define AUD_PLL_CLK0_LPCG 0x59d20000
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#define AUD_PLL_CLK1_LPCG 0x59d30000
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#define AUD_MCLKOUT0_LPCG 0x59d50000
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#define AUD_MCLKOUT1_LPCG 0x59d60000
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#define AUD_EDMA_1_LPCG 0x59df0000
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/* Connectivity SS */
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#define USDHC_0_LPCG 0x5B200000
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#define USDHC_1_LPCG 0x5B210000
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#define USDHC_2_LPCG 0x5B220000
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#define ENET_0_LPCG 0x5B230000
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#define ENET_1_LPCG 0x5B240000
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#define DTCP_LPCG 0x5B250000
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#define MLB_LPCG 0x5B260000
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#define USB_2_LPCG 0x5B270000
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#define USB_3_LPCG 0x5B280000
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#define NAND_LPCG 0x5B290000
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#define EDMA_LPCG 0x5B2A0000
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/* CM40 SS */
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#define CM40_I2C_LPCG 0x37630000
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/* CM41 SS */
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#define CM41_I2C_LPCG 0x3B630000
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#endif
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