897 lines
32 KiB
C
897 lines
32 KiB
C
/*
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* Copyright 2018 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
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#define _ASM_ARCH_IMX8MM_CLOCK_H
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/* Mainly for compatible to imx common code. */
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_IPG_CLK,
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MXC_CSPI_CLK,
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MXC_ESDHC_CLK,
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MXC_ESDHC2_CLK,
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MXC_ESDHC3_CLK,
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MXC_I2C_CLK,
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MXC_UART_CLK,
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MXC_QSPI_CLK,
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};
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enum pll_clocks {
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ANATOP_ARM_PLL,
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ANATOP_VPU_PLL,
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ANATOP_GPU_PLL,
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ANATOP_SYSTEM_PLL1,
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ANATOP_SYSTEM_PLL2,
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ANATOP_SYSTEM_PLL3,
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ANATOP_AUDIO_PLL1,
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ANATOP_AUDIO_PLL2,
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ANATOP_VIDEO_PLL,
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ANATOP_DRAM_PLL,
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};
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enum clk_slice_type {
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CORE_CLOCK_SLICE,
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BUS_CLOCK_SLICE,
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IP_CLOCK_SLICE,
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AHB_CLOCK_SLICE,
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IPG_CLOCK_SLICE,
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CORE_SEL_CLOCK_SLICE,
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DRAM_SEL_CLOCK_SLICE,
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};
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enum clk_root_index {
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ARM_A53_CLK_ROOT = 0,
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ARM_M4_CLK_ROOT = 1,
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VPU_A53_CLK_ROOT = 2,
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GPU3D_CLK_ROOT = 3,
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GPU2D_CLK_ROOT = 4,
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MAIN_AXI_CLK_ROOT = 16,
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ENET_AXI_CLK_ROOT = 17,
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NAND_USDHC_BUS_CLK_ROOT = 18,
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VPU_BUS_CLK_ROOT = 19,
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DISPLAY_AXI_CLK_ROOT = 20,
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DISPLAY_APB_CLK_ROOT = 21,
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DISPLAY_RTRM_CLK_ROOT = 22,
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USB_BUS_CLK_ROOT = 23,
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GPU_AXI_CLK_ROOT = 24,
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GPU_AHB_CLK_ROOT = 25,
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NOC_CLK_ROOT = 26,
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NOC_APB_CLK_ROOT = 27,
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AHB_CLK_ROOT = 32,
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/* TODO: IPG Not sure */
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IPG_CLK_ROOT = 33,
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AUDIO_AHB_CLK_ROOT = 34,
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MIPI_DSI_ESC_RX_CLK_ROOT = 36,
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DRAM_SEL_CFG = 48,
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CORE_SEL_CFG = 49,
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DRAM_ALT_CLK_ROOT = 64,
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DRAM_APB_CLK_ROOT = 65,
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VPU_G1_CLK_ROOT = 66,
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VPU_G2_CLK_ROOT = 67,
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DISPLAY_DTRC_CLK_ROOT = 68,
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DISPLAY_DC8000_CLK_ROOT = 69,
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PCIE_CTRL_CLK_ROOT = 70,
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PCIE_PHY_CLK_ROOT = 71,
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PCIE_AUX_CLK_ROOT = 72,
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DC_PIXEL_CLK_ROOT = 73,
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LCDIF_PIXEL_CLK_ROOT = 74,
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SAI1_CLK_ROOT = 75,
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SAI2_CLK_ROOT = 76,
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SAI3_CLK_ROOT = 77,
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SAI4_CLK_ROOT = 78,
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SAI5_CLK_ROOT = 79,
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SAI6_CLK_ROOT = 80,
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SPDIF1_CLK_ROOT = 81,
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SPDIF2_CLK_ROOT = 82,
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ENET_REF_CLK_ROOT = 83,
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ENET_TIMER_CLK_ROOT = 84,
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ENET_PHY_REF_CLK_ROOT = 85,
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NAND_CLK_ROOT = 86,
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QSPI_CLK_ROOT = 87,
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USDHC1_CLK_ROOT = 88,
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USDHC2_CLK_ROOT = 89,
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I2C1_CLK_ROOT = 90,
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I2C2_CLK_ROOT = 91,
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I2C3_CLK_ROOT = 92,
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I2C4_CLK_ROOT = 93,
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UART1_CLK_ROOT = 94,
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UART2_CLK_ROOT = 95,
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UART3_CLK_ROOT = 96,
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UART4_CLK_ROOT = 97,
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USB_CORE_REF_CLK_ROOT = 98,
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USB_PHY_REF_CLK_ROOT = 99,
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GIC_CLK_ROOT = 100,
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ECSPI1_CLK_ROOT = 101,
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ECSPI2_CLK_ROOT = 102,
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PWM1_CLK_ROOT = 103,
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PWM2_CLK_ROOT = 104,
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PWM3_CLK_ROOT = 105,
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PWM4_CLK_ROOT = 106,
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GPT1_CLK_ROOT = 107,
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GPT2_CLK_ROOT = 108,
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GPT3_CLK_ROOT = 109,
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GPT4_CLK_ROOT = 110,
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GPT5_CLK_ROOT = 111,
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GPT6_CLK_ROOT = 112,
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TRACE_CLK_ROOT = 113,
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WDOG_CLK_ROOT = 114,
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WRCLK_CLK_ROOT = 115,
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IPP_DO_CLKO1 = 116,
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IPP_DO_CLKO2 = 117,
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MIPI_DSI_CORE_CLK_ROOT = 118,
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MIPI_DSI_PHY_REF_CLK_ROOT = 119,
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MIPI_DSI_DBI_CLK_ROOT = 120,
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USDHC3_CLK_ROOT = 121,
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MIPI_CSI1_CORE_CLK_ROOT = 122,
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MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
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MIPI_CSI1_ESC_CLK_ROOT = 124,
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MIPI_CSI2_CORE_CLK_ROOT = 125,
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MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
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MIPI_CSI2_ESC_CLK_ROOT = 127,
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PCIE2_CTRL_CLK_ROOT = 128,
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PCIE2_PHY_CLK_ROOT = 129,
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PCIE2_AUX_CLK_ROOT = 130,
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ECSPI3_CLK_ROOT = 131,
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PDM_CLK_ROOT = 132,
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VPU_H1_CLK_ROOT = 133,
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CLK_ROOT_MAX,
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};
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enum clk_root_src {
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OSC_24M_CLK,
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ARM_PLL_CLK,
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DRAM_PLL1_CLK,
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VIDEO_PLL2_CLK,
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VPU_PLL_CLK,
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GPU_PLL_CLK,
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SYSTEM_PLL1_800M_CLK,
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SYSTEM_PLL1_400M_CLK,
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SYSTEM_PLL1_266M_CLK,
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SYSTEM_PLL1_200M_CLK,
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SYSTEM_PLL1_160M_CLK,
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SYSTEM_PLL1_133M_CLK,
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SYSTEM_PLL1_100M_CLK,
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SYSTEM_PLL1_80M_CLK,
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SYSTEM_PLL1_40M_CLK,
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SYSTEM_PLL2_1000M_CLK,
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SYSTEM_PLL2_500M_CLK,
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SYSTEM_PLL2_333M_CLK,
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SYSTEM_PLL2_250M_CLK,
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SYSTEM_PLL2_200M_CLK,
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SYSTEM_PLL2_166M_CLK,
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SYSTEM_PLL2_125M_CLK,
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SYSTEM_PLL2_100M_CLK,
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SYSTEM_PLL2_50M_CLK,
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SYSTEM_PLL3_CLK,
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AUDIO_PLL1_CLK,
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AUDIO_PLL2_CLK,
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VIDEO_PLL_CLK,
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OSC_32K_CLK,
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EXT_CLK_1,
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EXT_CLK_2,
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EXT_CLK_3,
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EXT_CLK_4,
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OSC_HDMI_CLK
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};
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enum clk_ccgr_index {
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CCGR_DVFS = 0,
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CCGR_ANAMIX = 1,
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CCGR_CPU = 2,
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CCGR_CSU = 3,
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CCGR_DEBUG = 4,
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CCGR_DDR1 = 5,
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CCGR_ECSPI1 = 7,
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CCGR_ECSPI2 = 8,
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CCGR_ECSPI3 = 9,
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CCGR_ENET1 = 10,
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CCGR_GPIO1 = 11,
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CCGR_GPIO2 = 12,
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CCGR_GPIO3 = 13,
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CCGR_GPIO4 = 14,
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CCGR_GPIO5 = 15,
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CCGR_GPT1 = 16,
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CCGR_GPT2 = 17,
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CCGR_GPT3 = 18,
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CCGR_GPT4 = 19,
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CCGR_GPT5 = 20,
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CCGR_GPT6 = 21,
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CCGR_HS = 22,
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CCGR_I2C1 = 23,
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CCGR_I2C2 = 24,
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CCGR_I2C3 = 25,
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CCGR_I2C4 = 26,
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CCGR_IOMUX = 27,
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CCGR_IOMUX1 = 28,
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CCGR_IOMUX2 = 29,
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CCGR_IOMUX3 = 30,
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CCGR_IOMUX4 = 31,
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CCGR_SNVSMIX_IPG_CLK = 32,
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CCGR_MU = 33,
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CCGR_OCOTP = 34,
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CCGR_OCRAM = 35,
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CCGR_OCRAM_S = 36,
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CCGR_PCIE = 37,
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CCGR_PERFMON1 = 38,
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CCGR_PERFMON2 = 39,
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CCGR_PWM1 = 40,
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CCGR_PWM2 = 41,
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CCGR_PWM3 = 42,
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CCGR_PWM4 = 43,
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CCGR_QOS = 44,
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CCGR_QOS_DISPMIX = 45,
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CCGR_QOS_ETHENET = 46,
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CCGR_QSPI = 47,
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CCGR_RAWNAND = 48,
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CCGR_RDC = 49,
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CCGR_ROM = 50,
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CCGR_SAI1 = 51,
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CCGR_SAI2 = 52,
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CCGR_SAI3 = 53,
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CCGR_SAI4 = 54,
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CCGR_SAI5 = 55,
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CCGR_SAI6 = 56,
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CCGR_SCTR = 57,
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CCGR_SDMA1 = 58,
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CCGR_SDMA2 = 59,
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CCGR_SEC_DEBUG = 60,
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CCGR_SEMA1 = 61,
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CCGR_SEMA2 = 62,
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CCGR_SIM_DISPLAY = 63,
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CCGR_SIM_ENET = 64,
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CCGR_SIM_M = 65,
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CCGR_SIM_MAIN = 66,
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CCGR_SIM_S = 67,
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CCGR_SIM_WAKEUP = 68,
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CCGR_SIM_HSIO = 69,
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CCGR_SIM_VPU = 70,
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CCGR_SNVS = 71,
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CCGR_TRACE = 72,
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CCGR_UART1 = 73,
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CCGR_UART2 = 74,
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CCGR_UART3 = 75,
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CCGR_UART4 = 76,
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CCGR_USB_MSCALE_PL301 = 77,
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CCGR_GPU3D = 79,
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CCGR_USDHC1 = 81,
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CCGR_USDHC2 = 82,
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CCGR_WDOG1 = 83,
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CCGR_WDOG2 = 84,
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CCGR_WDOG3 = 85,
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CCGR_VPUG1 = 86,
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CCGR_GPU_BUS = 87,
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CCGR_VPUH1 = 89,
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CCGR_VPUG2 = 90,
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CCGR_PDM = 91,
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CCGR_GIC = 92,
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CCGR_DISPMIX = 93,
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CCGR_USDHC3 = 94,
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CCGR_SDMA3 = 95,
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CCGR_XTAL = 96,
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CCGR_PLL = 97,
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CCGR_TEMP_SENSOR = 98,
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CCGR_VPUMIX_BUS = 99,
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CCGR_GPU2D = 102,
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CCGR_MAX
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};
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enum clk_src_index {
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CLK_SRC_CKIL_SYNC_REQ = 0,
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CLK_SRC_ARM_PLL_EN = 1,
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CLK_SRC_GPU_PLL_EN = 2,
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CLK_SRC_VPU_PLL_EN = 3,
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CLK_SRC_DRAM_PLL_EN = 4,
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CLK_SRC_SYSTEM_PLL1_EN = 5,
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CLK_SRC_SYSTEM_PLL2_EN = 6,
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CLK_SRC_SYSTEM_PLL3_EN = 7,
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CLK_SRC_AUDIO_PLL1_EN = 8,
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CLK_SRC_AUDIO_PLL2_EN = 9,
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CLK_SRC_VIDEO_PLL1_EN = 10,
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CLK_SRC_RESERVED = 11,
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CLK_SRC_ARM_PLL = 12,
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CLK_SRC_GPU_PLL = 13,
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CLK_SRC_VPU_PLL = 14,
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CLK_SRC_DRAM_PLL = 15,
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CLK_SRC_SYSTEM_PLL1_800M = 16,
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CLK_SRC_SYSTEM_PLL1_400M = 17,
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CLK_SRC_SYSTEM_PLL1_266M = 18,
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CLK_SRC_SYSTEM_PLL1_200M = 19,
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CLK_SRC_SYSTEM_PLL1_160M = 20,
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CLK_SRC_SYSTEM_PLL1_133M = 21,
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CLK_SRC_SYSTEM_PLL1_100M = 22,
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CLK_SRC_SYSTEM_PLL1_80M = 23,
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CLK_SRC_SYSTEM_PLL1_40M = 24,
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CLK_SRC_SYSTEM_PLL2_1000M = 25,
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CLK_SRC_SYSTEM_PLL2_500M = 26,
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CLK_SRC_SYSTEM_PLL2_333M = 27,
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CLK_SRC_SYSTEM_PLL2_250M = 28,
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CLK_SRC_SYSTEM_PLL2_200M = 29,
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CLK_SRC_SYSTEM_PLL2_166M = 30,
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CLK_SRC_SYSTEM_PLL2_125M = 31,
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CLK_SRC_SYSTEM_PLL2_100M = 32,
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CLK_SRC_SYSTEM_PLL2_50M = 33,
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CLK_SRC_SYSTEM_PLL3 = 34,
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CLK_SRC_AUDIO_PLL1 = 35,
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CLK_SRC_AUDIO_PLL2 = 36,
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CLK_SRC_VIDEO_PLL1 = 37,
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};
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enum root_pre_div {
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CLK_ROOT_PRE_DIV1 = 0,
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CLK_ROOT_PRE_DIV2,
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CLK_ROOT_PRE_DIV3,
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CLK_ROOT_PRE_DIV4,
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CLK_ROOT_PRE_DIV5,
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CLK_ROOT_PRE_DIV6,
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CLK_ROOT_PRE_DIV7,
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CLK_ROOT_PRE_DIV8,
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};
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enum root_post_div {
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CLK_ROOT_POST_DIV1 = 0,
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CLK_ROOT_POST_DIV2,
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CLK_ROOT_POST_DIV3,
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CLK_ROOT_POST_DIV4,
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CLK_ROOT_POST_DIV5,
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CLK_ROOT_POST_DIV6,
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CLK_ROOT_POST_DIV7,
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CLK_ROOT_POST_DIV8,
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CLK_ROOT_POST_DIV9,
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CLK_ROOT_POST_DIV10,
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CLK_ROOT_POST_DIV11,
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CLK_ROOT_POST_DIV12,
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CLK_ROOT_POST_DIV13,
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CLK_ROOT_POST_DIV14,
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CLK_ROOT_POST_DIV15,
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CLK_ROOT_POST_DIV16,
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CLK_ROOT_POST_DIV17,
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CLK_ROOT_POST_DIV18,
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CLK_ROOT_POST_DIV19,
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CLK_ROOT_POST_DIV20,
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CLK_ROOT_POST_DIV21,
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CLK_ROOT_POST_DIV22,
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CLK_ROOT_POST_DIV23,
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CLK_ROOT_POST_DIV24,
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CLK_ROOT_POST_DIV25,
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CLK_ROOT_POST_DIV26,
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CLK_ROOT_POST_DIV27,
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CLK_ROOT_POST_DIV28,
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CLK_ROOT_POST_DIV29,
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CLK_ROOT_POST_DIV30,
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CLK_ROOT_POST_DIV31,
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CLK_ROOT_POST_DIV32,
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CLK_ROOT_POST_DIV33,
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CLK_ROOT_POST_DIV34,
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CLK_ROOT_POST_DIV35,
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CLK_ROOT_POST_DIV36,
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CLK_ROOT_POST_DIV37,
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CLK_ROOT_POST_DIV38,
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CLK_ROOT_POST_DIV39,
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CLK_ROOT_POST_DIV40,
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CLK_ROOT_POST_DIV41,
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CLK_ROOT_POST_DIV42,
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CLK_ROOT_POST_DIV43,
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CLK_ROOT_POST_DIV44,
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CLK_ROOT_POST_DIV45,
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CLK_ROOT_POST_DIV46,
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CLK_ROOT_POST_DIV47,
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CLK_ROOT_POST_DIV48,
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CLK_ROOT_POST_DIV49,
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CLK_ROOT_POST_DIV50,
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CLK_ROOT_POST_DIV51,
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CLK_ROOT_POST_DIV52,
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CLK_ROOT_POST_DIV53,
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CLK_ROOT_POST_DIV54,
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CLK_ROOT_POST_DIV55,
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CLK_ROOT_POST_DIV56,
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CLK_ROOT_POST_DIV57,
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CLK_ROOT_POST_DIV58,
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CLK_ROOT_POST_DIV59,
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CLK_ROOT_POST_DIV60,
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CLK_ROOT_POST_DIV61,
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CLK_ROOT_POST_DIV62,
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CLK_ROOT_POST_DIV63,
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CLK_ROOT_POST_DIV64,
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};
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struct clk_root_map {
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enum clk_root_index entry;
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enum clk_slice_type slice_type;
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u32 slice_index;
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u8 src_mux[8];
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};
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struct ccm_ccgr {
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u32 ccgr;
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u32 ccgr_set;
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u32 ccgr_clr;
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u32 ccgr_tog;
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};
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struct ccm_root {
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u32 target_root;
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u32 target_root_set;
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u32 target_root_clr;
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u32 target_root_tog;
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u32 misc;
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u32 misc_set;
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u32 misc_clr;
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u32 misc_tog;
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u32 nm_post;
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u32 nm_post_root_set;
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u32 nm_post_root_clr;
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u32 nm_post_root_tog;
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u32 nm_pre;
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u32 nm_pre_root_set;
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u32 nm_pre_root_clr;
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u32 nm_pre_root_tog;
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u32 db_post;
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u32 db_post_root_set;
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u32 db_post_root_clr;
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u32 db_post_root_tog;
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u32 db_pre;
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u32 db_pre_root_set;
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u32 db_pre_root_clr;
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u32 db_pre_root_tog;
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u32 reserved[4];
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u32 access_ctrl;
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u32 access_ctrl_root_set;
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u32 access_ctrl_root_clr;
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u32 access_ctrl_root_tog;
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};
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struct ccm_reg {
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u32 reserved_0[4096];
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struct ccm_ccgr ccgr_array[192];
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u32 reserved_1[3328];
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struct ccm_root core_root[5];
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u32 reserved_2[352];
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struct ccm_root bus_root[12];
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u32 reserved_3[128];
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struct ccm_root ahb_ipg_root[4];
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u32 reserved_4[384];
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struct ccm_root dram_sel;
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struct ccm_root core_sel;
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u32 reserved_5[448];
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struct ccm_root ip_root[78];
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};
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enum dram_pll_out_val {
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DRAM_PLL_OUT_100M,
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DRAM_PLL_OUT_167M,
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DRAM_PLL_OUT_266M,
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DRAM_PLL_OUT_667M,
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DRAM_PLL_OUT_400M,
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DRAM_PLL_OUT_600M,
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DRAM_PLL_OUT_750M,
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DRAM_PLL_OUT_800M,
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};
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enum dram_bypassclk_val {
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DRAM_BYPASSCLK_100M,
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DRAM_BYPASSCLK_250M,
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DRAM_BYPASSCLK_400M,
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};
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|
|
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#define AUDIO_PLL1_GNRL_CTL (0x30360000)
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#define AUDIO_PLL1_FDIV_CTL0 (0x30360004)
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#define AUDIO_PLL1_FDIV_CTL1 (0x30360008)
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#define AUDIO_PLL1_SSCG_CTL (0x3036000c)
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#define AUDIO_PLL1_MNIT_CTL (0x30360010)
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#define AUDIO_PLL2_GNRL_CTL (0x30360014)
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#define AUDIO_PLL2_FDIV_CTL0 (0x30360018)
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#define AUDIO_PLL2_FDIV_CTL1 (0x3036001c)
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#define AUDIO_PLL2_SSCG_CTL (0x30360020)
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#define AUDIO_PLL2_MNIT_CTL (0x30360024)
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#define VIDEO_PLL1_GNRL_CTL (0x30360028)
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#define VIDEO_PLL1_FDIV_CTL0 (0x3036002c)
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#define VIDEO_PLL1_FDIV_CTL1 (0x30360030)
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#define VIDEO_PLL1_SSCG_CTL (0x30360034)
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#define VIDEO_PLL1_MNIT_CTL (0x30360038)
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#define DRAM_PLL_GNRL_CTL (0x30360050)
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#define DRAM_PLL_FDIV_CTL0 (0x30360054)
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#define DRAM_PLL_FDIV_CTL1 (0x30360058)
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#define DRAM_PLL_SSCG_CTL (0x3036005c)
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#define DRAM_PLL_MNIT_CTL (0x30360060)
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#define GPU_PLL_GNRL_CTL (0x30360064)
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#define GPU_PLL_DIV_CTL (0x30360068)
|
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#define GPU_PLL_LOCKED_CTL (0x3036006c)
|
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#define GPU_PLL_MNIT_CTL (0x30360070)
|
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#define VPU_PLL_GNRL_CTL (0x30360074)
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#define VPU_PLL_DIV_CTL (0x30360078)
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#define VPU_PLL_LOCKED_CTL (0x3036007c)
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#define VPU_PLL_MNIT_CTL (0x30360080)
|
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#define ARM_PLL_GNRL_CTL (0x30360084)
|
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#define ARM_PLL_DIV_CTL (0x30360088)
|
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#define ARM_PLL_LOCKED_CTL (0x3036008c)
|
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#define ARM_PLL_MNIT_CTL (0x30360090)
|
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#define SYS_PLL1_GNRL_CTL (0x30360094)
|
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#define SYS_PLL1_DIV_CTL (0x30360098)
|
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#define SYS_PLL1_LOCKED_CTL (0x3036009c)
|
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#define SYS_PLL1_MNIT_CTL (0x30360100)
|
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#define SYS_PLL2_GNRL_CTL (0x30360104)
|
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#define SYS_PLL2_DIV_CTL (0x30360108)
|
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#define SYS_PLL2_LOCKED_CTL (0x3036010c)
|
|
#define SYS_PLL2_MNIT_CTL (0x30360110)
|
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#define SYS_PLL3_GNRL_CTL (0x30360114)
|
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#define SYS_PLL3_DIV_CTL (0x30360118)
|
|
#define SYS_PLL3_LOCKED_CTL (0x3036011c)
|
|
#define SYS_PLL3_MNIT_CTL (0x30360120)
|
|
#define ANAMIX_MISC_CTL (0x30360124)
|
|
#define DIGPROG (0x30360800)
|
|
|
|
#define INTPLL_LOCK_MASK BIT(31)
|
|
#define INTPLL_LOCK_SEL_MASK BIT(29)
|
|
#define INTPLL_EXT_BYPASS_MASK BIT(28)
|
|
#define INTPLL_DIV20_CLKE_MASK BIT(27)
|
|
#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
|
|
#define INTPLL_DIV10_CLKE_MASK BIT(25)
|
|
#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
|
|
#define INTPLL_DIV8_CLKE_MASK BIT(23)
|
|
#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
|
|
#define INTPLL_DIV6_CLKE_MASK BIT(21)
|
|
#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
|
|
#define INTPLL_DIV5_CLKE_MASK BIT(19)
|
|
#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
|
|
#define INTPLL_DIV4_CLKE_MASK BIT(17)
|
|
#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
|
|
#define INTPLL_DIV3_CLKE_MASK BIT(15)
|
|
#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
|
|
#define INTPLL_DIV2_CLKE_MASK BIT(13)
|
|
#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
|
|
#define INTPLL_CLKE_MASK BIT(11)
|
|
#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
|
|
#define INTPLL_RST_MASK BIT(9)
|
|
#define INTPLL_RST_OVERRIDE_MASK BIT(8)
|
|
#define INTPLL_BYPASS_MASK BIT(4)
|
|
#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
|
|
#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
|
|
|
|
#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
|
|
#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
|
|
#define INTPLL_MAIN_DIV_SHIFT 12
|
|
#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
|
|
#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
|
|
#define INTPLL_PRE_DIV_SHIFT 4
|
|
#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
|
|
#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
|
|
#define INTPLL_POST_DIV_SHIFT 0
|
|
|
|
#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
|
|
#define INTPLL_LOCK_CON_DLY_SHIFT 4
|
|
#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
|
|
#define INTPLL_LOCK_CON_OUT_SHIFT 2
|
|
#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
|
|
#define INTPLL_LOCK_CON_IN_SHIFT 0
|
|
|
|
#define INTPLL_LRD_EN_MASK BIT(21)
|
|
#define INTPLL_FOUT_MASK BIT(20)
|
|
#define INTPLL_AFC_SEL_MASK BIT(19)
|
|
#define INTPLL_PBIAS_CTRL_MASK BIT(18)
|
|
#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
|
|
#define INTPLL_AFCINIT_SEL_MASK BIT(16)
|
|
#define INTPLL_FSEL_MASK BIT(14)
|
|
#define INTPLL_FEED_EN_MASK BIT(13)
|
|
#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
|
|
#define INTPLL_AFC_EN_MASK BIT(2)
|
|
#define INTPLL_ICP_MASK GENMASK(1, 0)
|
|
|
|
/* CORE clock generation: i ranges from 0 to 4 */
|
|
#define CCM_CORE_CLK_ROOT_GEN_TAGET(i) (0x30388000UL + 0x80 * (i) + 0x00)
|
|
#define CCM_CORE_CLK_ROOT_GEN_TAGET_SET(i) (0x30388000UL + 0x80 * (i) + 0x04)
|
|
#define CCM_CORE_CLK_ROOT_GEN_TAGET_CLR(i) (0x30388000UL + 0x80 * (i) + 0x08)
|
|
#define CCM_CORE_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x0c)
|
|
#define CCM_CORE_CLK_ROOT_GEN_MISC(i) (0x30388000UL + 0x80 * (i) + 0x10)
|
|
#define CCM_CORE_CLK_ROOT_GEN_MISC_SET(i) (0x30388000UL + 0x80 * (i) + 0x14)
|
|
#define CCM_CORE_CLK_ROOT_GEN_MISC_CLR(i) (0x30388000UL + 0x80 * (i) + 0x18)
|
|
#define CCM_CORE_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x1c)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_POST(i) (0x30388000UL + 0x80 * (i) + 0x20)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_POST_SET(i) (0x30388000UL + 0x80 * (i) + 0x24)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30388000UL + 0x80 * (i) + 0x28)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x2c)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_PRE(i) (0x30388000UL + 0x80 * (i) + 0x30)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30388000UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30388000UL + 0x80 * (i) + 0x38)
|
|
#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_POST(i) (0x30388000UL + 0x80 * (i) + 0x40)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_POST_SET(i) (0x30388000UL + 0x80 * (i) + 0x44)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30388000UL + 0x80 * (i) + 0x48)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30388000UL + 0x80 * (i) + 0x4c)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_PRE(i) (0x30388000UL + 0x80 * (i) + 0x50)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30388000UL + 0x80 * (i) + 0x54)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30388000UL + 0x80 * (i) + 0x58)
|
|
#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x5c)
|
|
#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL(i) (0x30388000UL + 0x80 * (i) + 0x70)
|
|
#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30388000UL + 0x80 * (i) + 0x74)
|
|
#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30388000UL + 0x80 * (i) + 0x78)
|
|
#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30388000UL + 0x80 * (i) +0x7c)
|
|
|
|
|
|
/* BUS clock generation: i ranges from 0 to 11 */
|
|
#define CCM_BUS_CLK_ROOT_GEN_TAGET(i) (0x30388800UL + 0x80 * (i) + 0x00)
|
|
#define CCM_BUS_CLK_ROOT_GEN_TAGET_SET(i) (0x30388800UL + 0x80 * (i) + 0x04)
|
|
#define CCM_BUS_CLK_ROOT_GEN_TAGET_CLR(i) (0x30388800UL + 0x80 * (i) + 0x08)
|
|
#define CCM_BUS_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x0c)
|
|
#define CCM_BUS_CLK_ROOT_GEN_MISC(i) (0x30388800UL + 0x80 * (i) + 0x10)
|
|
#define CCM_BUS_CLK_ROOT_GEN_MISC_SET(i) (0x30388800UL + 0x80 * (i) + 0x14)
|
|
#define CCM_BUS_CLK_ROOT_GEN_MISC_CLR(i) (0x30388800UL + 0x80 * (i) + 0x18)
|
|
#define CCM_BUS_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x1c)
|
|
#define CCM_BUS CLK_ROOT_GEN_NM_POST(i) (0x30388800UL + 0x80 * (i) + 0x20)
|
|
#define CCM_BUS_CLK_ROOT_GEN_NM_POST_SET(i) (0x30388800UL + 0x80 * (i) + 0x24)
|
|
#define CCM_BUS_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30388800UL + 0x80 * (i) + 0x28)
|
|
#define CCM_BUS_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x2c)
|
|
#define CCM_BUS_CLK_ROOT_GEN_NM_PRE(i) (0x30388800UL + 0x80 * (i) + 0x30)
|
|
#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30388800UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30388800UL + 0x80 * (i) + 0x38)
|
|
#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_POST(i) (0x30388800UL + 0x80 * (i) + 0x40)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_POST_SET(i) (0x30388800UL + 0x80 * (i) + 0x44)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30388800UL + 0x80 * (i) + 0x48)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30388800UL + 0x80 * (i) + 0x4c)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_PRE(i) (0x30388800UL + 0x80 * (i) + 0x50)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30388800UL + 0x80 * (i) + 0x54)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30388800UL + 0x80 * (i) + 0x58)
|
|
#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x5c)
|
|
#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL(i) (0x30388800UL + 0x80 * (i) + 0x70)
|
|
#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30388800UL + 0x80 * (i) + 0x74)
|
|
#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30388800UL + 0x80 * (i) + 0x78)
|
|
#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x7c)
|
|
|
|
/* IP clock generation: i ranges from 0 to 77 */
|
|
#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (0x3038a000UL + 0x80 * (i) + 0x00)
|
|
#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (0x3038a000UL + 0x80 * (i) + 0x04)
|
|
#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x08)
|
|
#define CCM_IP_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x0c)
|
|
#define CCM_IP_CLK_ROOT_GEN_MISC(i) (0x3038a000UL + 0x80 * (i) + 0x10)
|
|
#define CCM_IP_CLK_ROOT_GEN_MISC_SET(i) (0x3038a000UL + 0x80 * (i) + 0x14)
|
|
#define CCM_IP_CLK_ROOT_GEN_MISC_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x18)
|
|
#define CCM_IP_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x1c)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_POST(i) (0x3038a000UL + 0x80 * (i) + 0x20)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_POST_SET(i) (0x3038a000UL + 0x80 * (i) + 0x24)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_POST_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x28)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x2c)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_PRE(i) (0x3038a000UL + 0x80 * (i) + 0x30)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_PRE_SET(i) (0x3038a000UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x38)
|
|
#define CCM_IP_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_POST(i) (0x3038a000UL + 0x80 * (i) + 0x40)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_POST_SET(i) (0x3038a000UL + 0x80 * (i) + 0x44)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_POST_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x48)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x3038a000UL + 0x80 * (i) + 0x4c)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_PRE(i) (0x3038a000UL + 0x80 * (i) + 0x50)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_PRE_SET(i) (0x3038a000UL + 0x80 * (i) + 0x54)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x58)
|
|
#define CCM_IP_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x5c)
|
|
#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL(i) (0x3038a000UL + 0x80 * (i) + 0x70)
|
|
#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x3038a000UL + 0x80 * (i) + 0x74)
|
|
#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x78)
|
|
#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x7c)
|
|
|
|
/* AHB clock generation: i ranges from 0 to 1*/
|
|
#define CCM_AHB_CLK_ROOT_GEN_TAGET(i) (0x30389000UL + 0x80 * (i) + 0x00)
|
|
#define CCM_AHB_CLK_ROOT_GEN_TAGET_SET(i) (0x30389000UL + 0x80 * (i) + 0x04)
|
|
#define CCM_AHB_CLK_ROOT_GEN_TAGET_CLR(i) (0x30389000UL + 0x80 * (i) + 0x08)
|
|
#define CCM_AHB_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x0c)
|
|
#define CCM_AHB_CLK_ROOT_GEN_MISC(i) (0x30389000UL + 0x80 * (i) + 0x10)
|
|
#define CCM_AHB_CLK_ROOT_GEN_MISC_SET(i) (0x30389000UL + 0x80 * (i) + 0x14)
|
|
#define CCM_AHB_CLK_ROOT_GEN_MISC_CLR(i) (0x30389000UL + 0x80 * (i) + 0x18)
|
|
#define CCM_AHB_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x1c)
|
|
#define CCM_AHB CLK_ROOT_GEN_NM_POST(i) (0x30389000UL + 0x80 * (i) + 0x20)
|
|
#define CCM_AHB_CLK_ROOT_GEN_NM_POST_SET(i) (0x30389000UL + 0x80 * (i) + 0x24)
|
|
#define CCM_AHB_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30389000UL + 0x80 * (i) + 0x28)
|
|
#define CCM_AHB_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x2c)
|
|
#define CCM_AHB_CLK_ROOT_GEN_NM_PRE(i) (0x30389000UL + 0x80 * (i) + 0x30)
|
|
#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30389000UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30389000UL + 0x80 * (i) + 0x38)
|
|
#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x3c)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_POST(i) (0x30389000UL + 0x80 * (i) + 0x40)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_POST_SET(i) (0x30389000UL + 0x80 * (i) + 0x44)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30389000UL + 0x80 * (i) + 0x48)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30389000UL + 0x80 * (i) + 0x4c)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_PRE(i) (0x30389000UL + 0x80 * (i) + 0x50)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30389000UL + 0x80 * (i) + 0x54)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30389000UL + 0x80 * (i) + 0x58)
|
|
#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x5c)
|
|
#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL(i) (0x30389000UL + 0x80 * (i) + 0x70)
|
|
#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30389000UL + 0x80 * (i) + 0x74)
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#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30389000UL + 0x80 * (i) + 0x78)
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#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x7c)
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/* IPG clock generation: i ranges from 0 to 1*/
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#define CCM_IPG_CLK_ROOT_GEN_TAGET(i) (0x30389080UL + 0x80 * (i) + 0x00)
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#define CCM_IPG_CLK_ROOT_GEN_TAGET_SET(i) (0x30389080UL + 0x80 * (i) + 0x04)
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#define CCM_IPG_CLK_ROOT_GEN_TAGET_CLR(i) (0x30389080UL + 0x80 * (i) + 0x08)
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#define CCM_IPG_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x0c)
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#define CCM_IPG_CLK_ROOT_GEN_MISC(i) (0x30389080UL + 0x80 * (i) + 0x10)
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#define CCM_IPG_CLK_ROOT_GEN_MISC_SET(i) (0x30389080UL + 0x80 * (i) + 0x14)
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#define CCM_IPG_CLK_ROOT_GEN_MISC_CLR(i) (0x30389080UL + 0x80 * (i) + 0x18)
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#define CCM_IPG_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x1c)
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#define CCM_IPG CLK_ROOT_GEN_NM_POST(i) (0x30389080UL + 0x80 * (i) + 0x20)
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#define CCM_IPG_CLK_ROOT_GEN_NM_POST_SET(i) (0x30389080UL + 0x80 * (i) + 0x24)
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#define CCM_IPG_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30389080UL + 0x80 * (i) + 0x28)
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#define CCM_IPG_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x2c)
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#define CCM_IPG_CLK_ROOT_GEN_NM_PRE(i) (0x30389080UL + 0x80 * (i) + 0x30)
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#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30389080UL + 0x80 * (i) + 0x3c)
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#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30389080UL + 0x80 * (i) + 0x38)
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#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x3c)
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#define CCM_IPG_CLK_ROOT_GEN_DB_POST(i) (0x30389080UL + 0x80 * (i) + 0x40)
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#define CCM_IPG_CLK_ROOT_GEN_DB_POST_SET(i) (0x30389080UL + 0x80 * (i) + 0x44)
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#define CCM_IPG_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30389080UL + 0x80 * (i) + 0x48)
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#define CCM_IPG_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30389080UL + 0x80 * (i) + 0x4c)
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#define CCM_IPG_CLK_ROOT_GEN_DB_PRE(i) (0x30389080UL + 0x80 * (i) + 0x50)
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#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30389080UL + 0x80 * (i) + 0x54)
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#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30389080UL + 0x80 * (i) + 0x58)
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#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x5c)
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#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL(i) (0x30389080UL + 0x80 * (i) + 0x70)
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#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30389080UL + 0x80 * (i) + 0x74)
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#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30389080UL + 0x80 * (i) + 0x78)
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#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x7c)
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/* CORE_SEL clock generation */
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#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET (0x30389880UL + 0x00)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_SET (0x30389880UL + 0x04)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_CLR (0x30389880UL + 0x08)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_TOGGLE (0x30389880UL + 0x0c)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC (0x30389880UL + 0x10)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_SET (0x30389880UL + 0x14)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_CLR (0x30389880UL + 0x18)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_TOGGLE (0x30389880UL + 0x1c)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST (0x30389880UL + 0x20)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_SET (0x30389880UL + 0x24)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_CLR (0x30389880UL + 0x28)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_TOGGLE (0x30389880UL + 0x2c)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE (0x30389880UL + 0x30)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_SET (0x30389880UL + 0x3c)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_CLR (0x30389880UL + 0x38)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_TOGGLE (0x30389880UL + 0x3c)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST (0x30389880UL + 0x40)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_SET (0x30389880UL + 0x44)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_CLR (0x30389880UL + 0x48)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_TOGGL (0x30389880UL + 0x4c)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE (0x30389880UL + 0x50)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_SET (0x30389880UL + 0x54)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_CLR (0x30389880UL + 0x58)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_TOGGLE (0x30389880UL + 0x5c)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL (0x30389880UL + 0x70)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_SET (0x30389880UL + 0x74)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_CLR (0x30389880UL + 0x78)
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#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_TOGGLE (0x30389880UL + 0x7c)
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/* DRAM_SEL clock generation */
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET (0x30389800UL + 0x00)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_SET (0x30389800UL + 0x04)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_CLR (0x30389800UL + 0x08)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_TOGGLE (0x30389800UL + 0x0c)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC (0x30389800UL + 0x10)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_SET (0x30389800UL + 0x14)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_CLR (0x30389800UL + 0x18)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_TOGGLE (0x30389800UL + 0x1c)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST (0x30389800UL + 0x20)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_SET (0x30389800UL + 0x24)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_CLR (0x30389800UL + 0x28)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_TOGGLE (0x30389800UL + 0x2c)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE (0x30389800UL + 0x30)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_SET (0x30389800UL + 0x3c)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_CLR (0x30389800UL + 0x38)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_TOGGLE (0x30389800UL + 0x3c)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST (0x30389800UL + 0x40)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_SET (0x30389800UL + 0x44)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_CLR (0x30389800UL + 0x48)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_TOGGL (0x30389800UL + 0x4c)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE (0x30389800UL + 0x50)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_SET (0x30389800UL + 0x54)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_CLR (0x30389800UL + 0x58)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_TOGGLE (0x30389800UL + 0x5c)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL (0x30389800UL + 0x70)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_SET (0x30389800UL + 0x74)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_CLR (0x30389800UL + 0x78)
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#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_TOGGLE (0x30389800UL + 0x7c)
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/* CCGR: i ranges from 0 to 191 */
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#define CCM_CCGR(i) (0x30384000UL + 0x10 * (i) + 0x00)
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#define CCM_CCGR_SET(i) (0x30384000UL + 0x10 * (i) + 0x04)
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#define CCM_CCGR_CLR(i) (0x30384000UL + 0x10 * (i) + 0x08)
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#define CCM_CCGR_TOGGLE(i) (0x30384000UL + 0x10 * (i) + 0x0c)
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/* Source Control: i ranges from 0 to 38 */
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#define CCM_SRC(i) (0x30380800UL + 0x10 * (i) + 0x00)
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#define CCM_SRC_SET(i) (0x30380800UL + 0x10 * (i) + 0x04)
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#define CCM_SRC_CLR(i) (0x30380800UL + 0x10 * (i) + 0x08)
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#define CCM_SRC_TOGGLE(i) (0x30380800UL + 0x10 * (i) + 0x0c)
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|
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/* Observe Control: i ranges from 0 to 7 */
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#define CCM_OBSERVE(i) (0x30380400UL + 0x10 * (i) + 0x00)
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#define CCM_OBSERVE_SET(i) (0x30380400UL + 0x10 * (i) + 0x04)
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#define CCM_OBSERVE_CLR(i) (0x30380400UL + 0x10 * (i) + 0x08)
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#define CCM_OBSERVE_TOGGLE(i) (0x30380400UL + 0x10 * (i) + 0x0c)
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/* Generic Control: i ranges from 0 to 9 */
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#define CCM_GEN(i) (0x30380000UL + 0x10 * (i) + 0x00)
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#define CCM_GEN_SET(i) (0x30380000UL + 0x10 * (i) + 0x04)
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#define CCM_GEN_CLR(i) (0x30380000UL + 0x10 * (i) + 0x08)
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#define CCM_GEN_TOGGLE(i) (0x30380000UL + 0x10 * (i) + 0x0c)
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|
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#define CCGR_CLK_ON_MASK 0x03
|
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#define CLK_SRC_ON_MASK 0x03
|
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|
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#define CLK_ROOT_ON BIT(28)
|
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#define CLK_ROOT_OFF (0 << 28)
|
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#define CLK_ROOT_ENABLE_MASK BIT(28)
|
|
#define CLK_ROOT_ENABLE_SHIFT 28
|
|
#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
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|
|
/* For SEL, only use 1 bit */
|
|
#define CLK_ROOT_SRC_MUX_MASK 0x07000000
|
|
#define CLK_ROOT_SRC_MUX_SHIFT 24
|
|
#define CLK_ROOT_SRC_0 0x00000000
|
|
#define CLK_ROOT_SRC_1 0x01000000
|
|
#define CLK_ROOT_SRC_2 0x02000000
|
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#define CLK_ROOT_SRC_3 0x03000000
|
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#define CLK_ROOT_SRC_4 0x04000000
|
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#define CLK_ROOT_SRC_5 0x05000000
|
|
#define CLK_ROOT_SRC_6 0x06000000
|
|
#define CLK_ROOT_SRC_7 0x07000000
|
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|
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#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
|
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#define CLK_ROOT_PRE_DIV_SHIFT 16
|
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#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
|
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|
|
#define CLK_ROOT_AUDO_SLOW_EN 0x1000
|
|
|
|
#define CLK_ROOT_AUDO_DIV_MASK 0x700
|
|
#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
|
|
#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
|
|
|
|
/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
|
|
#define CLK_ROOT_POST_DIV_MASK 0x3f
|
|
#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
|
|
#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
|
|
#define CLK_ROOT_POST_DIV_SHIFT 0
|
|
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
|
|
|
|
/* TODO check more */
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
|
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
|
|
#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
|
|
#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
|
|
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
|
|
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
|
|
|
|
enum enet_freq {
|
|
ENET_25MHZ = 0,
|
|
ENET_50MHZ,
|
|
ENET_125MHZ,
|
|
};
|
|
void dram_pll_init(enum dram_pll_out_val pll_val);
|
|
void dram_enable_bypass(enum dram_bypassclk_val clk_val);
|
|
void dram_disable_bypass(void);
|
|
u32 imx_get_fecclk(void);
|
|
u32 imx_get_uartclk(void);
|
|
int clock_init(void);
|
|
u32 mxc_get_clock(enum mxc_clock clk);
|
|
int clock_enable(enum clk_ccgr_index index, bool enable);
|
|
int clock_root_enabled(enum clk_root_index clock_id);
|
|
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
|
|
enum root_post_div post_div, enum clk_root_src clock_src);
|
|
int clock_set_target_val(enum clk_root_index clock_id, u32 val);
|
|
int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
|
|
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
|
|
int clock_get_postdiv(enum clk_root_index clock_id,
|
|
enum root_post_div *post_div);
|
|
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
|
|
void mxs_set_lcdclk(u32 base_addr, u32 freq);
|
|
int set_clk_qspi(void);
|
|
void enable_ocotp_clk(unsigned char enable);
|
|
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
|
|
int set_clk_enet(enum enet_freq type);
|
|
void hab_caam_clock_enable(unsigned char enable);
|
|
void enable_usboh3_clk(unsigned char enable);
|
|
#endif
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