489 lines
13 KiB
C
489 lines
13 KiB
C
/*
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* board/renesas/blanche/blanche.c
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* This file is blanche board support.
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*
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* Copyright (C) 2016 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/sh_sdhi.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <mmc.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct pin_db {
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u32 addr; /* register address */
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u32 mask; /* mask value */
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u32 val; /* setting value */
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};
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#define PMMR 0xE6060000
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#define GPSR0 0xE6060004
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#define GPSR1 0xE6060008
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#define GPSR4 0xE6060014
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#define GPSR5 0xE6060018
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#define GPSR6 0xE606001C
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#define GPSR7 0xE6060020
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#define GPSR8 0xE6060024
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#define GPSR9 0xE6060028
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#define GPSR10 0xE606002C
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#define GPSR11 0xE6060030
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#define IPSR6 0xE6060058
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#define PUPR2 0xE6060108
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#define PUPR3 0xE606010C
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#define PUPR4 0xE6060110
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#define PUPR5 0xE6060114
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#define PUPR7 0xE606011C
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#define PUPR9 0xE6060124
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#define PUPR10 0xE6060128
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#define PUPR11 0xE606012C
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#define CPG_PLL1CR 0xE6150028
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#define CPG_PLL3CR 0xE61500DC
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#define SetREG(x) \
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writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
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#define SetGuardREG(x) \
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{ \
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u32 val; \
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val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
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writel(~val, PMMR); \
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writel(val, (x)->addr); \
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}
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struct pin_db pin_guard[] = {
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{ GPSR0, 0xFFFFFFFF, 0x0BFFFFFF },
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{ GPSR1, 0xFFFFFFFF, 0x002FFFFF },
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{ GPSR4, 0xFFFFFFFF, 0x00000FFF },
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{ GPSR5, 0xFFFFFFFF, 0x00010FFF },
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{ GPSR6, 0xFFFFFFFF, 0x00010FFF },
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{ GPSR7, 0xFFFFFFFF, 0x00010FFF },
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{ GPSR8, 0xFFFFFFFF, 0x00010FFF },
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{ GPSR9, 0xFFFFFFFF, 0x00010FFF },
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{ GPSR10, 0xFFFFFFFF, 0x04006000 },
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{ GPSR11, 0xFFFFFFFF, 0x303FEFE0 },
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{ IPSR6, 0xFFFFFFFF, 0x0002000E },
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};
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struct pin_db pin_tbl[] = {
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{ PUPR2, 0xFFFFFFFF, 0x00000000 },
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{ PUPR3, 0xFFFFFFFF, 0x0803FF40 },
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{ PUPR4, 0xFFFFFFFF, 0x0000FFFF },
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{ PUPR5, 0xFFFFFFFF, 0x00010FFF },
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{ PUPR7, 0xFFFFFFFF, 0x0001AFFF },
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{ PUPR9, 0xFFFFFFFF, 0x0001CFFF },
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{ PUPR10, 0xFFFFFFFF, 0xC0438001 },
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{ PUPR11, 0xFFFFFFFF, 0x0FC00007 },
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};
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void pin_init(void)
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{
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struct pin_db *db;
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for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
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SetGuardREG(db);
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}
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for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
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SetREG(db);
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}
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}
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#define s_init_wait(cnt) \
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({ \
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volatile u32 i = 0x10000 * cnt; \
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while (i > 0) \
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i--; \
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})
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 cpu_type;
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cpu_type = rmobile_get_cpu_type();
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if (cpu_type == 0x4A) {
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writel(0x4D000000, CPG_PLL1CR);
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writel(0x4F000000, CPG_PLL3CR);
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}
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* QoS(Quality-of-Service) Init */
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qos_init();
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/* SCIF Init */
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pin_init();
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#if defined(CONFIG_MTD_NOR_FLASH)
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struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
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struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
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/* LBSC */
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writel(0x00000020, &lbsc->cs0ctrl);
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writel(0x00000020, &lbsc->cs1ctrl);
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writel(0x00002020, &lbsc->ecs0ctrl);
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writel(0x00002020, &lbsc->ecs1ctrl);
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writel(0x2A103320, &lbsc->cswcr0);
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writel(0x2A103320, &lbsc->cswcr1);
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writel(0x19102110, &lbsc->ecswcr0);
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writel(0x19102110, &lbsc->ecswcr1);
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/* DBSC3 */
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s_init_wait(10);
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writel(0x0000A55A, &dbsc3_0->dbpdlck);
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writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */
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writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
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writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */
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/* Stop Auto-Calibration */
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x80000000, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
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/* PLLCR: PLL Control Register */
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writel(0x00000006, &dbsc3_0->dbpdrga);
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writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440
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/* DXCCR: DATX8 Common Configuration Register */
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writel(0x0000000F, &dbsc3_0->dbpdrga);
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writel(0x00181EE4, &dbsc3_0->dbpdrgd);
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/* DSGCR :DDR System General Configuration Register */
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writel(0x00000010, &dbsc3_0->dbpdrga);
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writel(0xF00464DB, &dbsc3_0->dbpdrgd);
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writel(0x00000061, &dbsc3_0->dbpdrga);
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writel(0x0000008D, &dbsc3_0->dbpdrgd);
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/* Re-Execute ZQ calibration */
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000073, &dbsc3_0->dbpdrgd);
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writel(0x00000007, &dbsc3_0->dbkind);
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writel(0x0F030A02, &dbsc3_0->dbconf0);
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writel(0x00000001, &dbsc3_0->dbphytype);
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writel(0x00000000, &dbsc3_0->dbbl);
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writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11
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writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8
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writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0
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writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11
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writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11
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writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39
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writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28
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writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6
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writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32
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writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8
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writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12
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writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9
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writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18
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writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208
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writel(0x00140005, &dbsc3_0->dbtr14);
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writel(0x00050004, &dbsc3_0->dbtr15);
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writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */
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writel(0x000C0000, &dbsc3_0->dbtr17);
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writel(0x00000300, &dbsc3_0->dbtr18);
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writel(0x00000040, &dbsc3_0->dbtr19);
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writel(0x00000001, &dbsc3_0->dbrnk0);
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writel(0x00020001, &dbsc3_0->dbadj0);
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writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */
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writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */
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writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
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while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
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writel(0x00000011, &dbsc3_0->dbdficnt);
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/* PGCR1 :PHY General Configuration Register 1 */
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writel(0x00000003, &dbsc3_0->dbpdrga);
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writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */
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/* PGCR2: PHY General Configuration Registers 2 */
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writel(0x00000023, &dbsc3_0->dbpdrga);
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writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
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writel(0x00000011, &dbsc3_0->dbpdrga);
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writel(0x1000040B, &dbsc3_0->dbpdrgd);
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/* DTPR0 :DRAM Timing Parameters Register 0 */
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writel(0x00000012, &dbsc3_0->dbpdrga);
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writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
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/* DTPR1 :DRAM Timing Parameters Register 1 */
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writel(0x00000013, &dbsc3_0->dbpdrga);
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writel(0x1A868400, &dbsc3_0->dbpdrgd);
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/* DTPR2 ::DRAM Timing Parameters Register 2 */
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writel(0x00000014, &dbsc3_0->dbpdrga);
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writel(0x300214D8, &dbsc3_0->dbpdrgd);
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/* MR0 :Mode Register 0 */
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writel(0x00000015, &dbsc3_0->dbpdrga);
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writel(0x00000D70, &dbsc3_0->dbpdrgd);
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/* MR1 :Mode Register 1 */
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writel(0x00000016, &dbsc3_0->dbpdrga);
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writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */
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/* MR2 :Mode Register 2 */
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writel(0x00000017, &dbsc3_0->dbpdrga);
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writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */
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/* VREF(ZQCAL) */
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writel(0x0000001A, &dbsc3_0->dbpdrga);
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writel(0x910035C7, &dbsc3_0->dbpdrgd);
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/* PGSR0 :PHY General Status Registers 0 */
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writel(0x00000004, &dbsc3_0->dbpdrga);
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while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
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/* DRAM Init (set MRx etc) */
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000181, &dbsc3_0->dbpdrgd);
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/* CKE = H */
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writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
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/* PGSR0 :PHY General Status Registers 0 */
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writel(0x00000004, &dbsc3_0->dbpdrga);
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while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
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/* RAM ACC Training */
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x0000FE01, &dbsc3_0->dbpdrgd);
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/* Bus control 0 */
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writel(0x00000000, &dbsc3_0->dbbs0cnt1);
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/* DDR3 Calibration set */
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writel(0x01004C20, &dbsc3_0->dbcalcnf);
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/* DDR3 Calibration timing */
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writel(0x014000AA, &dbsc3_0->dbcaltr);
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/* Refresh */
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writel(0x00000140, &dbsc3_0->dbrfcnf0);
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writel(0x00081860, &dbsc3_0->dbrfcnf1);
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writel(0x00010000, &dbsc3_0->dbrfcnf2);
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/* PGSR0 :PHY General Status Registers 0 */
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writel(0x00000004, &dbsc3_0->dbpdrga);
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while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
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/* Enable Auto-Refresh */
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writel(0x00000001, &dbsc3_0->dbrfen);
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/* Permit DDR-Access */
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writel(0x00000001, &dbsc3_0->dbacen);
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/* This locks the access to the PHY unit registers */
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writel(0x00000000, &dbsc3_0->dbpdlck);
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#endif /* CONFIG_MTD_NOR_FLASH */
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}
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#define TMU0_MSTP125 (1 << 25)
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#define SCIF0_MSTP721 (1 << 21)
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#define SDHI0_MSTP314 (1 << 14)
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#define QSPI_MSTP917 (1 << 17)
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int board_early_init_f(void)
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{
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/* TMU0 */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/* SCIF0 */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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/* SDHI0 */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
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/* QSPI */
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
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return 0;
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}
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7792_pinmux_init();
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gpio_request(GPIO_FN_D0, NULL);
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gpio_request(GPIO_FN_D1, NULL);
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gpio_request(GPIO_FN_D2, NULL);
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gpio_request(GPIO_FN_D3, NULL);
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gpio_request(GPIO_FN_D4, NULL);
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gpio_request(GPIO_FN_D5, NULL);
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gpio_request(GPIO_FN_D6, NULL);
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gpio_request(GPIO_FN_D7, NULL);
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gpio_request(GPIO_FN_D8, NULL);
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gpio_request(GPIO_FN_D9, NULL);
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gpio_request(GPIO_FN_D10, NULL);
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gpio_request(GPIO_FN_D11, NULL);
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gpio_request(GPIO_FN_D12, NULL);
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gpio_request(GPIO_FN_D13, NULL);
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gpio_request(GPIO_FN_D14, NULL);
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gpio_request(GPIO_FN_D15, NULL);
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gpio_request(GPIO_FN_A0, NULL);
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gpio_request(GPIO_FN_A1, NULL);
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gpio_request(GPIO_FN_A2, NULL);
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gpio_request(GPIO_FN_A3, NULL);
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gpio_request(GPIO_FN_A4, NULL);
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gpio_request(GPIO_FN_A5, NULL);
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gpio_request(GPIO_FN_A6, NULL);
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gpio_request(GPIO_FN_A7, NULL);
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gpio_request(GPIO_FN_A8, NULL);
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gpio_request(GPIO_FN_A9, NULL);
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gpio_request(GPIO_FN_A10, NULL);
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gpio_request(GPIO_FN_A11, NULL);
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gpio_request(GPIO_FN_A12, NULL);
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gpio_request(GPIO_FN_A13, NULL);
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gpio_request(GPIO_FN_A14, NULL);
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gpio_request(GPIO_FN_A15, NULL);
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gpio_request(GPIO_FN_A16, NULL);
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gpio_request(GPIO_FN_A17, NULL);
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gpio_request(GPIO_FN_A18, NULL);
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gpio_request(GPIO_FN_A19, NULL);
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#if !defined(CONFIG_MTD_NOR_FLASH)
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gpio_request(GPIO_FN_MOSI_IO0, NULL);
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gpio_request(GPIO_FN_MISO_IO1, NULL);
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gpio_request(GPIO_FN_IO2, NULL);
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gpio_request(GPIO_FN_IO3, NULL);
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gpio_request(GPIO_FN_SPCLK, NULL);
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gpio_request(GPIO_FN_SSL, NULL);
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#else /* CONFIG_MTD_NOR_FLASH */
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gpio_request(GPIO_FN_A20, NULL);
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gpio_request(GPIO_FN_A21, NULL);
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gpio_request(GPIO_FN_A22, NULL);
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gpio_request(GPIO_FN_A23, NULL);
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gpio_request(GPIO_FN_A24, NULL);
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gpio_request(GPIO_FN_A25, NULL);
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#endif /* CONFIG_MTD_NOR_FLASH */
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gpio_request(GPIO_FN_CS1_A26, NULL);
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gpio_request(GPIO_FN_EX_CS0, NULL);
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gpio_request(GPIO_FN_EX_CS1, NULL);
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gpio_request(GPIO_FN_BS, NULL);
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gpio_request(GPIO_FN_RD, NULL);
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gpio_request(GPIO_FN_WE0, NULL);
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gpio_request(GPIO_FN_WE1, NULL);
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gpio_request(GPIO_FN_EX_WAIT0, NULL);
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gpio_request(GPIO_FN_IRQ0, NULL);
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gpio_request(GPIO_FN_IRQ2, NULL);
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gpio_request(GPIO_FN_IRQ3, NULL);
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gpio_request(GPIO_FN_CS0, NULL);
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/* Init timer */
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timer_init();
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return 0;
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}
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/*
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Added for BLANCHE(R-CarV2H board)
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*/
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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#define STR_ENV_ETHADDR "ethaddr"
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struct eth_device *dev;
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uchar eth_addr[6];
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
|
|
dev = eth_get_dev_by_index(0);
|
|
if (dev) {
|
|
eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
|
|
} else {
|
|
printf("blanche: Couldn't get eth device\n");
|
|
rc = -1;
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
return rc;
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
int ret = -ENODEV;
|
|
|
|
#ifdef CONFIG_SH_SDHI
|
|
gpio_request(GPIO_FN_SD0_DAT0, NULL);
|
|
gpio_request(GPIO_FN_SD0_DAT1, NULL);
|
|
gpio_request(GPIO_FN_SD0_DAT2, NULL);
|
|
gpio_request(GPIO_FN_SD0_DAT3, NULL);
|
|
gpio_request(GPIO_FN_SD0_CLK, NULL);
|
|
gpio_request(GPIO_FN_SD0_CMD, NULL);
|
|
gpio_request(GPIO_FN_SD0_CD, NULL);
|
|
|
|
gpio_request(GPIO_GP_11_12, NULL);
|
|
gpio_direction_output(GPIO_GP_11_12, 1); /* power on */
|
|
|
|
|
|
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
|
|
SH_SDHI_QUIRK_16BIT_BUF);
|
|
|
|
if (ret)
|
|
return ret;
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
|
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct rmobile_sysinfo sysinfo = {
|
|
CONFIG_RMOBILE_BOARD_STRING
|
|
};
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
}
|
|
|
|
static const struct sh_serial_platdata serial_platdata = {
|
|
.base = SCIF0_BASE,
|
|
.type = PORT_SCIF,
|
|
.clk = 14745600,
|
|
.clk_mode = EXT_CLK,
|
|
};
|
|
|
|
U_BOOT_DEVICE(blanche_serials) = {
|
|
.name = "serial_sh",
|
|
.platdata = &serial_platdata,
|
|
};
|