65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/mach-imx/sci/sci.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <imx8_hsio.h>
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int sata_init(void)
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{
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int ret;
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u32 val, i = 0;
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printf("start sata init\n");
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writel(0x22222222, GPR_LPCG_PHYX2APB_0_APB);
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writel(0x22222222, GPR_LPCG_PHYX1_APB);
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setbits_le32(0x5F130008, BIT(21));
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setbits_le32(0x5F130008, BIT(23));
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/* PHY_MODE to SATA100Mhz ref clk */
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setbits_le32(HW_PHYX1_CTRL0_ADDR, BIT(19));
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/*
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* bit 0 rx ena, bit 1 tx ena, bit 11 fast_init,
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* bit12 PHY_X1_EPCS_SEL 1.
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*/
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setbits_le32(HW_MISC_CTRL0_ADDR, HW_MISC_CTRL0_IOB_RXENA
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| HW_MISC_CTRL0_PHY_X1_EPCS_SEL);
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clrbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_PHY_RESET);
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setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_PHY_RESET);
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setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET);
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udelay(1);
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clrbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET);
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setbits_le32(HW_SATA_CTRL0_ADDR, HW_SATA_CTRL0_RESET);
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setbits_le32(HW_PHYX1_CTRL0_ADDR, HW_PHYX1_CTRL0_APB_RSTN);
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for (i = 0; i < 100; i++) {
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val = readl(HW_PHYX1_STTS0_ADDR);
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val &= HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK;
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if (val == HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK)
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break;
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udelay(1);
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}
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if (val != HW_PHYX1_STTS0_LANE0_TX_PLL_LOCK) {
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printf("TX PLL is not locked.\n");
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return -ENODEV;
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}
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ret = ahci_init((void __iomem *)AHCI_BASE_ADDR);
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if (ret)
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return ret;
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scsi_scan(1);
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return 0;
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}
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