271 lines
7.1 KiB
C
271 lines
7.1 KiB
C
/*
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* Copyright 2017 NXP
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*
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* NXP i.MX8 USB HOST xHCI Controller (Cadence IP)
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*
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* Author: Peter Chen <peter.chen@nxp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <usb.h>
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#include <malloc.h>
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#include <linux/compat.h>
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#include "xhci.h"
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#include <usb/imx8_usb3_reg_def.h>
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#include <dm.h>
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#include <power-domain.h>
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#include <asm/arch/clock.h>
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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/* According to UG CH 3.1.1 Bring-up Sequence */
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static void imx_usb3_phy_init(void)
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{
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writel(0x0830, PHY_PMA_CMN_CTRL1);
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writel(0x10, TB_ADDR_CMN_DIAG_HSCLK_SEL);
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writel(0x00F0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR);
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writel(0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR);
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writel(0x00D0, TB_ADDR_CMN_PLL0_INTDIV);
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writel(0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV);
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writel(0x0034, TB_ADDR_CMN_PLL0_HIGH_THR);
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writel(0x1ee, TB_ADDR_CMN_PLL0_SS_CTRL1);
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writel(0x7F03, TB_ADDR_CMN_PLL0_SS_CTRL2);
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writel(0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG);
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writel(0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD);
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writel(0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD);
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writel(0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD);
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writel(0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE);
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writel(0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE);
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writel(0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG);
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writel(0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE);
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writel(0x000a, TB_ADDR_CMN_PSM_CLK_CTRL);
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writel(0x139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR);
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writel(0xbefc, TB_ADDR_XCVR_PSM_RCTRL);
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writel(0x7799, TB_ADDR_TX_PSC_A0);
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writel(0x7798, TB_ADDR_TX_PSC_A1);
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writel(0x509b, TB_ADDR_TX_PSC_A2);
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writel(0x3, TB_ADDR_TX_DIAG_ECTRL_OVRD);
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writel(0x5098, TB_ADDR_TX_PSC_A3);
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writel(0x2090, TB_ADDR_TX_PSC_CAL);
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writel(0x2090, TB_ADDR_TX_PSC_RDY);
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writel(0xA6FD, TB_ADDR_RX_PSC_A0);
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writel(0xA6FD, TB_ADDR_RX_PSC_A1);
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writel(0xA410, TB_ADDR_RX_PSC_A2);
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writel(0x2410, TB_ADDR_RX_PSC_A3);
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writel(0x23FF, TB_ADDR_RX_PSC_CAL);
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writel(0x2010, TB_ADDR_RX_PSC_RDY);
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writel(0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000);
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writel(0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY);
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writel(0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR);
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writel(0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR);
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writel(0x0000, TB_ADDR_RX_SAMP_DAC_CTRL);
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writel(0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE);
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writel(0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2);
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writel(0x0480, TB_ADDR_RX_DIAG_BS_TM);
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writel(0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1);
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writel(0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4);
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writel(0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0);
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writel(0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0);
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writel(0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6);
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writel(0x8000, TB_ADDR_RX_DIAG_RXFE_TM3);
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writel(0x0003, TB_ADDR_RX_DIAG_RXFE_TM4);
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writel(0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE);
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writel(0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3);
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writel(0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY);
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writel(0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE);
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writel(0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR);
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writel(0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR);
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writel(0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR);
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writel(0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR);
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writel(0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR);
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writel(0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR);
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writel(0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR);
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writel(0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR);
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writel(0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR);
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writel(0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR);
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writel(0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR);
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writel(0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR);
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writel(0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR);
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writel(0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR);
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/* Change rx detect parameter */
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writel(0x960, TB_ADDR_TX_RCVDET_EN_TMR);
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writel(0x01e0, TB_ADDR_TX_RCVDET_ST_TMR);
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writel(0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR);
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udelay(10);
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/* force rx detect */
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/* writel(0xc000, TB_ADDR_TX_RCVDET_OVRD); */
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}
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void imx8_xhci_init(void)
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{
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u32 tmp_data;
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tmp_data = readl(USB3_SSPHY_STATUS);
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writel(tmp_data, USB3_SSPHY_STATUS);
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tmp_data = readl(USB3_SSPHY_STATUS);
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while ((tmp_data & 0xf0000000) != 0xf0000000) {
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printf("clkvld is incorrect = 0x%x\n", tmp_data);
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udelay(10);
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tmp_data = readl(USB3_SSPHY_STATUS);
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}
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tmp_data = readl(USB3_CORE_CTRL1);
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tmp_data = (tmp_data & 0xfffffff8) | 0x202;
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writel(tmp_data, USB3_CORE_CTRL1);
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tmp_data &= ~0x04000000; /* clear PHY apb reset */
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writel(tmp_data, USB3_CORE_CTRL1);
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imx_usb3_phy_init();
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tmp_data = readl(USB3_CORE_CTRL1);
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tmp_data &= ~0xfc000000; /* clear all sw_rst */
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writel(tmp_data, USB3_CORE_CTRL1);
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debug("wait xhci_power_on_ready\n");
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tmp_data = readl(USB3_CORE_STATUS);
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while (!(tmp_data & 0x1000))
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tmp_data = readl(USB3_CORE_STATUS);
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debug("xhci_power_on_ready\n");
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tmp_data = readl(USBSTS);
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debug("waiting CNR 0x%x\n", tmp_data);
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while (tmp_data & 0x800)
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tmp_data = readl(USBSTS);
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debug("check CNR has finished\n");
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}
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void imx8_xhci_reset(void)
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{
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/* Set CORE ctrl to default value, that all rst are hold */
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writel(0xfc000001, USB3_CORE_CTRL1);
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}
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#ifdef CONFIG_DM_USB
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static int xhci_imx8_probe(struct udevice *dev)
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{
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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int ret = 0;
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int len;
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/* Need to power on the PHY before access it */
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#if CONFIG_IS_ENABLED(POWER_DOMAIN)
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struct udevice phy_dev;
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struct power_domain pd;
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const void *blob = gd->fdt_blob;
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int offset = dev_of_offset(dev), phy_off;
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phy_off = fdtdec_lookup_phandle(blob,
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offset,
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"fsl,usbphy");
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if (phy_off < 0)
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return -EINVAL;
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phy_dev.node = offset_to_ofnode(phy_off);
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if (!power_domain_get(&phy_dev, &pd)) {
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if (power_domain_on(&pd))
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return -EINVAL;
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}
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#endif
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ret = board_usb_init(dev->seq, USB_INIT_HOST);
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if (ret != 0) {
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printf("Failed to initialize board for USB\n");
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return ret;
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}
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init_clk_usb3(dev->seq);
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imx8_xhci_init();
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hccr = (struct xhci_hccr *)HCIVERSION_CAPLENGTH;
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len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
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hcor = (struct xhci_hcor *)((uintptr_t) hccr + len);
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printf("XHCI-imx8 init hccr 0x%p and hcor 0x%p hc_length %d\n",
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(uint32_t *)hccr, (uint32_t *)hcor, len);
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return xhci_register(dev, hccr, hcor);
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}
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static int xhci_imx8_remove(struct udevice *dev)
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{
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int ret = xhci_deregister(dev);
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if (!ret)
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imx8_xhci_reset();
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board_usb_cleanup(dev->seq, USB_INIT_HOST);
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return ret;
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}
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static const struct udevice_id xhci_usb_ids[] = {
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{ .compatible = "fsl,imx8-usb3", },
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{ }
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};
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U_BOOT_DRIVER(xhci_imx8) = {
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.name = "xhci_imx8",
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.id = UCLASS_USB,
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.of_match = xhci_usb_ids,
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.probe = xhci_imx8_probe,
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.remove = xhci_imx8_remove,
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.ops = &xhci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct xhci_ctrl),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#else
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int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
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struct xhci_hcor **ret_hcor)
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{
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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int len, ret;
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ret = board_usb_init(index, USB_INIT_HOST);
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if (ret != 0) {
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printf("Failed to initialize board for USB\n");
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return ret;
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}
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init_clk_usb3(index);
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imx8_xhci_init();
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hccr = (struct xhci_hccr *)HCIVERSION_CAPLENGTH;
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len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
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hcor = (struct xhci_hcor *)((uintptr_t) hccr + len);
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printf("XHCI-imx8 init hccr 0x%p and hcor 0x%p hc_length %d\n",
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(uint32_t *)hccr, (uint32_t *)hcor, len);
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*ret_hccr = hccr;
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*ret_hcor = hcor;
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return 0;
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}
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void xhci_hcd_stop(int index)
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{
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imx8_xhci_reset();
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board_usb_cleanup(index, USB_INIT_HOST);
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}
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#endif
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