60fd0ed90a
The HDMI digital PLL, bus clock and core clock need to change to improve the firmware loading time. The clock are now set to 800 MHz for DPLL, 200 MHz for HDMI core, and 100 MHz for HDMI bus. Signed-off-by: Oliver Brown <oliver.brown@nxp.com> |
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| .. | ||
| hdp | ||
| Makefile | ||
| hdp.c | ||
| hdp_load.c | ||
| hdprx_load.c | ||
| imx8_hdmi.c | ||
| scfw_utils.h | ||