292 lines
6.9 KiB
C
292 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <dm/platform_data/pfe_dm_eth.h>
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#include <net.h>
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#include <linux/delay.h>
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#include <net/pfe_eth/pfe_eth.h>
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extern struct gemac_s gem_info[];
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#if defined(CONFIG_PHYLIB)
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#define MDIO_TIMEOUT 5000
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static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr,
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int reg_addr)
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{
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void *reg_base = bus->priv;
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u32 devadr;
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u32 phy;
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u32 reg_data;
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int timeout = MDIO_TIMEOUT;
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devadr = ((dev_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
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phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
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reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr);
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writel(reg_data, reg_base + EMAC_MII_DATA_REG);
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/*
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* wait for the MII interrupt
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*/
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while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
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if (timeout-- <= 0) {
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printf("Phy MDIO read/write timeout\n");
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return -1;
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}
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}
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/*
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* clear MII interrupt
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*/
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writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
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return 0;
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}
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static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
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int reg_addr)
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{
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void *reg_base = bus->priv;
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u32 reg;
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u32 phy;
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u32 reg_data;
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u16 val;
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int timeout = MDIO_TIMEOUT;
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if (dev_addr == MDIO_DEVAD_NONE) {
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reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
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EMAC_MII_DATA_RA_SHIFT);
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} else {
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pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
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reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
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EMAC_MII_DATA_RA_SHIFT);
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}
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phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
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if (dev_addr == MDIO_DEVAD_NONE)
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reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
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EMAC_MII_DATA_TA | phy | reg);
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else
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reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA |
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phy | reg);
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writel(reg_data, reg_base + EMAC_MII_DATA_REG);
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/*
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* wait for the MII interrupt
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*/
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while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
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if (timeout-- <= 0) {
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printf("Phy MDIO read/write timeout\n");
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return -1;
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}
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}
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/*
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* clear MII interrupt
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*/
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writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
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/*
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* it's now safe to read the PHY's register
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*/
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val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
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debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base,
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phy_addr, reg_addr, val);
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return val;
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}
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static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
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int reg_addr, u16 data)
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{
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void *reg_base = bus->priv;
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u32 reg;
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u32 phy;
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u32 reg_data;
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int timeout = MDIO_TIMEOUT;
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if (dev_addr == MDIO_DEVAD_NONE) {
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reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
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EMAC_MII_DATA_RA_SHIFT);
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} else {
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pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
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reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
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EMAC_MII_DATA_RA_SHIFT);
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}
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phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
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if (dev_addr == MDIO_DEVAD_NONE)
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reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
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EMAC_MII_DATA_TA | phy | reg | data);
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else
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reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA |
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phy | reg | data);
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writel(reg_data, reg_base + EMAC_MII_DATA_REG);
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/*
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* wait for the MII interrupt
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*/
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while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
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if (timeout-- <= 0) {
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printf("Phy MDIO read/write timeout\n");
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return -1;
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}
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}
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/*
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* clear MII interrupt
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*/
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writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
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reg_addr, data);
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return 0;
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}
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static void pfe_configure_serdes(struct pfe_eth_dev *priv)
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{
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struct mii_dev bus;
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int value, sgmii_2500 = 0;
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struct gemac_s *gem = priv->gem;
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if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
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sgmii_2500 = 1;
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/* PCS configuration done with corresponding GEMAC */
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bus.priv = gem_info[priv->gemac_port].gemac_base;
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pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
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pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
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pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
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pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
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/* Reset serdes */
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
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/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
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value = PHY_SGMII_IF_MODE_SGMII;
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if (!sgmii_2500)
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value |= PHY_SGMII_IF_MODE_AN;
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else
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value |= PHY_SGMII_IF_MODE_SGMII_GBT;
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
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/* Dev ability according to SGMII specification */
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value = PHY_SGMII_DEV_ABILITY_SGMII;
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
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/* These values taken from validation team */
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if (!sgmii_2500) {
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
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} else {
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x7);
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xa120);
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}
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/* Restart AN */
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value = PHY_SGMII_CR_DEF_VAL;
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if (!sgmii_2500)
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value |= PHY_SGMII_CR_RESET_AN;
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/* Disable Auto neg for 2.5G SGMII as it doesn't support auto neg*/
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if (sgmii_2500)
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value &= ~PHY_SGMII_ENABLE_AN;
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pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
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}
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int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
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{
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struct phy_device *phydev = NULL;
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struct udevice *dev = priv->dev;
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struct gemac_s *gem = priv->gem;
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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if (!gem->bus)
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return -1;
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/* Configure SGMII PCS */
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if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
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gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
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out_be32(&scfg->mdioselcr, 0x00000000);
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pfe_configure_serdes(priv);
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}
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mdelay(100);
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/* By this time on-chip SGMII initialization is done
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* we can switch mdio interface to external PHYs
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*/
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out_be32(&scfg->mdioselcr, 0x80000000);
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phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
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if (!phydev) {
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printf("phy_connect failed\n");
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return -ENODEV;
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}
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phy_config(phydev);
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priv->phydev = phydev;
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return 0;
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}
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#endif
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struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info)
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{
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struct mii_dev *bus;
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int ret;
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u32 mdio_speed;
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u32 pclk = 250000000;
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bus = mdio_alloc();
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if (!bus) {
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printf("mdio_alloc failed\n");
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return NULL;
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}
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bus->read = pfe_phy_read;
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bus->write = pfe_phy_write;
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/* MAC1 MDIO used to communicate with external PHYS */
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bus->priv = mdio_info->reg_base;
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sprintf(bus->name, mdio_info->name);
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/* configure mdio speed */
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mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
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mdio_speed |= EMAC_HOLDTIME(0x5);
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writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
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ret = mdio_register(bus);
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if (ret) {
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printf("mdio_register failed\n");
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free(bus);
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return NULL;
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}
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return bus;
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}
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void pfe_set_mdio(int dev_id, struct mii_dev *bus)
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{
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gem_info[dev_id].bus = bus;
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}
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void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
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{
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gem_info[dev_id].phy_address = phy_id;
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gem_info[dev_id].phy_mode = phy_mode;
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}
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