228 lines
4.0 KiB
ArmAsm
228 lines
4.0 KiB
ArmAsm
/*
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* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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/* DDR script */
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.macro imx7d_ddrphy_latency_setting
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ldr r2, =ANATOP_BASE_ADDR
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ldr r3, [r2, #0x800]
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and r3, r3, #0xFF
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cmp r3, #0x11
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bne NO_DELAY
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/*TO 1.1*/
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ldr r1, =0x00000dee
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str r1, [r0, #0x9c]
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ldr r1, =0x18181818
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str r1, [r0, #0x7c]
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ldr r1, =0x18181818
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str r1, [r0, #0x80]
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ldr r1, =0x40401818
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str r1, [r0, #0x84]
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ldr r1, =0x00000040
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str r1, [r0, #0x88]
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ldr r1, =0x40404040
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str r1, [r0, #0x6c]
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b TUNE_END
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NO_DELAY:
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/*TO 1.0*/
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ldr r1, =0x00000b24
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str r1, [r0, #0x9c]
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TUNE_END:
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.endm
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.macro imx7d_ddr_freq_setting
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ldr r2, =ANATOP_BASE_ADDR
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ldr r3, [r2, #0x800]
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and r3, r3, #0xFF
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cmp r3, #0x11
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bne FREQ_DEFAULT_533
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/* Change to 400Mhz for TO1.1 */
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ldr r0, =ANATOP_BASE_ADDR
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ldr r1, =0x70
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ldr r2, =0x00703021
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str r2, [r0, r1]
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ldr r1, =0x90
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ldr r2, =0x0
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str r2, [r0, r1]
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ldr r1, =0x70
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ldr r2, =0x00603021
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str r2, [r0, r1]
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ldr r3, =0x80000000
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wait_lock:
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ldr r2, [r0, r1]
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and r2, r3
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cmp r2, r3
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bne wait_lock
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x9880
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ldr r2, =0x1
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str r2, [r0, r1]
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FREQ_DEFAULT_533:
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.endm
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.macro imx7d_sabresd_ddr_setting
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imx7d_ddr_freq_setting
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/* Configure ocram_epdc */
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ldr r0, =IOMUXC_GPR_BASE_ADDR
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ldr r1, =0x4f400005
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str r1, [r0, #0x4]
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/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
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ldr r0, =ANATOP_BASE_ADDR
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ldr r1, =(0x1 << 30)
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str r1, [r0, #0x388]
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str r1, [r0, #0x384]
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ldr r0, =SRC_BASE_ADDR
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ldr r1, =0x2
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ldr r2, =0x1000
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str r1, [r0, r2]
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ldr r0, =DDRC_IPS_BASE_ADDR
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ldr r1, =0x01040001
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str r1, [r0]
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ldr r1, =0x80400003
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str r1, [r0, #0x1a0]
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ldr r1, =0x00100020
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str r1, [r0, #0x1a4]
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ldr r1, =0x80100004
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str r1, [r0, #0x1a8]
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ldr r1, =0x00400046
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str r1, [r0, #0x64]
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ldr r1, =0x1
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str r1, [r0, #0x490]
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ldr r1, =0x00020001
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str r1, [r0, #0xd0]
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ldr r1, =0x00690000
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str r1, [r0, #0xd4]
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ldr r1, =0x09300004
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str r1, [r0, #0xdc]
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ldr r1, =0x04080000
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str r1, [r0, #0xe0]
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ldr r1, =0x00100004
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str r1, [r0, #0xe4]
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ldr r1, =0x33f
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str r1, [r0, #0xf4]
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ldr r1, =0x09081109
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str r1, [r0, #0x100]
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ldr r1, =0x0007020d
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str r1, [r0, #0x104]
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ldr r1, =0x03040407
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str r1, [r0, #0x108]
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ldr r1, =0x00002006
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str r1, [r0, #0x10c]
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ldr r1, =0x04020205
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str r1, [r0, #0x110]
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ldr r1, =0x03030202
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str r1, [r0, #0x114]
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ldr r1, =0x00000803
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str r1, [r0, #0x120]
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ldr r1, =0x00800020
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str r1, [r0, #0x180]
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ldr r1, =0x02000100
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str r1, [r0, #0x184]
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ldr r1, =0x02098204
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str r1, [r0, #0x190]
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ldr r1, =0x00030303
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str r1, [r0, #0x194]
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ldr r1, =0x00000016
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str r1, [r0, #0x200]
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ldr r1, =0x00080808
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str r1, [r0, #0x204]
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ldr r1, =0x00000f0f
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str r1, [r0, #0x210]
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ldr r1, =0x07070707
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str r1, [r0, #0x214]
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ldr r1, =0x0f070707
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str r1, [r0, #0x218]
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ldr r1, =0x06000604
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str r1, [r0, #0x240]
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ldr r1, =0x00000001
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str r1, [r0, #0x244]
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ldr r0, =SRC_BASE_ADDR
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mov r1, #0x0
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ldr r2, =0x1000
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str r1, [r0, r2]
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ldr r0, =DDRPHY_IPS_BASE_ADDR
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ldr r1, =0x17420f40
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str r1, [r0]
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ldr r1, =0x10210100
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str r1, [r0, #0x4]
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ldr r1, =0x00060807
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str r1, [r0, #0x10]
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ldr r1, =0x1010007e
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str r1, [r0, #0xb0]
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imx7d_ddrphy_latency_setting
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ldr r1, =0x08080808
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str r1, [r0, #0x20]
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ldr r1, =0x08080808
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str r1, [r0, #0x30]
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ldr r1, =0x01000010
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str r1, [r0, #0x50]
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ldr r1, =0x0e407304
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str r1, [r0, #0xc0]
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ldr r1, =0x0e447304
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str r1, [r0, #0xc0]
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ldr r1, =0x0e447306
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str r1, [r0, #0xc0]
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wait_zq:
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ldr r1, [r0, #0xc4]
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tst r1, #0x1
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beq wait_zq
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ldr r1, =0x0e407304
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str r1, [r0, #0xc0]
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ldr r0, =CCM_BASE_ADDR
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mov r1, #0x0
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ldr r2, =0x4130
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str r1, [r0, r2]
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ldr r0, =IOMUXC_GPR_BASE_ADDR
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mov r1, #0x178
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str r1, [r0, #0x20]
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ldr r0, =CCM_BASE_ADDR
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mov r1, #0x2
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ldr r2, =0x4130
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str r1, [r0, r2]
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ldr r0, =DDRPHY_IPS_BASE_ADDR
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ldr r1, =0x0000000f
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str r1, [r0, #0x18]
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ldr r0, =DDRC_IPS_BASE_ADDR
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wait_stat:
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ldr r1, [r0, #0x4]
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tst r1, #0x1
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beq wait_stat
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.endm
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.macro imx7_clock_gating
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.endm
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.macro imx7_qos_setting
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.endm
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.macro imx7_ddr_setting
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imx7d_sabresd_ddr_setting
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.endm
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/* include the common plugin code here */
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#include <asm/arch/mx7_plugin.S>
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