277 lines
6.3 KiB
C
277 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019, Vaisala Oyj
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <i2c.h>
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#include <rtc.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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/*
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* RTC register addresses
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*/
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#define RTC_SEC_REG_ADDR 0x00
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#define RTC_MIN_REG_ADDR 0x01
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#define RTC_HR_REG_ADDR 0x02
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#define RTC_DAY_REG_ADDR 0x03
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#define RTC_DATE_REG_ADDR 0x04
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#define RTC_MON_REG_ADDR 0x05
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#define RTC_YR_REG_ADDR 0x06
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#define RTC_CTL_REG_ADDR 0x0e
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#define RTC_STAT_REG_ADDR 0x0f
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#define RTC_TEST_REG_ADDR 0x13
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/*
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* RTC control register bits
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*/
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#define RTC_CTL_BIT_A1IE BIT(0) /* Alarm 1 interrupt enable */
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#define RTC_CTL_BIT_A2IE BIT(1) /* Alarm 2 interrupt enable */
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#define RTC_CTL_BIT_INTCN BIT(2) /* Interrupt control */
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#define RTC_CTL_BIT_DOSC BIT(7) /* Disable Oscillator */
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/*
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* RTC status register bits
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*/
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#define RTC_STAT_BIT_A1F BIT(0) /* Alarm 1 flag */
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#define RTC_STAT_BIT_A2F BIT(1) /* Alarm 2 flag */
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#define RTC_STAT_BIT_EN32KHZ BIT(3) /* Enable 32KHz Output */
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#define RTC_STAT_BIT_BB32KHZ BIT(6) /* Battery backed 32KHz Output */
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#define RTC_STAT_BIT_OSF BIT(7) /* Oscillator stop flag */
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/*
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* RTC test register bits
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*/
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#define RTC_TEST_BIT_SWRST BIT(7) /* Software reset */
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#define RTC_DATE_TIME_REG_SIZE 7
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#define RTC_SRAM_START 0x14
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#define RTC_SRAM_END 0xFF
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#define RTC_SRAM_SIZE 236
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struct ds3232_priv_data {
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u8 max_register;
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u8 sram_start;
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int sram_size;
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};
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static int ds3232_rtc_read8(struct udevice *dev, unsigned int reg)
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{
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int ret;
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u8 buf;
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struct ds3232_priv_data *priv_data;
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priv_data = dev_get_priv(dev);
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if (!priv_data)
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return -EINVAL;
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if (reg > priv_data->max_register)
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return -EINVAL;
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ret = dm_i2c_read(dev, reg, &buf, sizeof(buf));
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if (ret < 0)
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return ret;
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return buf;
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}
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static int ds3232_rtc_write8(struct udevice *dev, unsigned int reg, int val)
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{
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u8 buf = (u8)val;
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struct ds3232_priv_data *priv_data;
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priv_data = dev_get_priv(dev);
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if (!priv_data)
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return -EINVAL;
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if (reg > priv_data->max_register)
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return -EINVAL;
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return dm_i2c_write(dev, reg, &buf, sizeof(buf));
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}
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static int reset_sram(struct udevice *dev)
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{
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int ret, sram_end, reg;
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struct ds3232_priv_data *priv_data;
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priv_data = dev_get_priv(dev);
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if (!priv_data)
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return -EINVAL;
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sram_end = priv_data->sram_start + priv_data->sram_size;
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for (reg = priv_data->sram_start; reg < sram_end; reg++) {
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ret = ds3232_rtc_write8(dev, reg, 0x00);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int verify_osc(struct udevice *dev)
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{
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int ret, rtc_status;
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ret = ds3232_rtc_read8(dev, RTC_STAT_REG_ADDR);
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if (ret < 0)
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return ret;
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rtc_status = ret;
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if (rtc_status & RTC_STAT_BIT_OSF) {
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dev_warn(dev,
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"oscillator discontinuity flagged, time unreliable\n");
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/*
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* In case OSC was off we cannot trust the SRAM data anymore.
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* Reset it to 0x00.
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*/
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ret = reset_sram(dev);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int ds3232_rtc_set(struct udevice *dev, const struct rtc_time *tm)
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{
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u8 buf[RTC_DATE_TIME_REG_SIZE];
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u8 is_century;
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if (tm->tm_year < 1900 || tm->tm_year > 2099)
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dev_warn(dev, "WARNING: year should be between 1900 and 2099!\n");
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is_century = (tm->tm_year >= 2000) ? 0x80 : 0;
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buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
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buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
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buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
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buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
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buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
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buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon) | is_century;
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buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
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return dm_i2c_write(dev, 0, buf, sizeof(buf));
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}
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static int ds3232_rtc_get(struct udevice *dev, struct rtc_time *tm)
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{
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int ret;
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u8 buf[RTC_DATE_TIME_REG_SIZE];
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u8 is_twelve_hr;
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u8 is_pm;
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u8 is_century;
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ret = verify_osc(dev);
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if (ret < 0)
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return ret;
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ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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/* Extract additional information for AM/PM and century */
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is_twelve_hr = buf[RTC_HR_REG_ADDR] & 0x40;
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is_pm = buf[RTC_HR_REG_ADDR] & 0x20;
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is_century = buf[RTC_MON_REG_ADDR] & 0x80;
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tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
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tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
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if (is_twelve_hr)
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tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x1F)
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+ (is_pm ? 12 : 0);
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else
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tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR]);
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tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] & 0x07) - 1);
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tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
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tm->tm_mon = bcd2bin((buf[RTC_MON_REG_ADDR] & 0x7F));
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tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR])
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+ (is_century ? 2000 : 1900);
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tm->tm_yday = 0;
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tm->tm_isdst = 0;
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return 0;
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}
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static int ds3232_rtc_reset(struct udevice *dev)
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{
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int ret;
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ret = reset_sram(dev);
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if (ret < 0)
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return ret;
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/*
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* From datasheet
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* (https://datasheets.maximintegrated.com/en/ds/DS3232M.pdf):
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*
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* The device reset occurs during the normal acknowledge time slot
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* following the receipt of the data byte carrying that
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* SWRST instruction a NACK occurs due to the resetting action.
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*
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* Therefore we don't verify the result of I2C write operation since it
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* will fail due the NACK.
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*/
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ds3232_rtc_write8(dev, RTC_TEST_REG_ADDR, RTC_TEST_BIT_SWRST);
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return 0;
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}
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static int ds3232_probe(struct udevice *dev)
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{
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int rtc_status;
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int ret;
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struct ds3232_priv_data *priv_data;
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priv_data = dev_get_priv(dev);
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if (!priv_data)
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return -EINVAL;
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priv_data->sram_start = RTC_SRAM_START;
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priv_data->max_register = RTC_SRAM_END;
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priv_data->sram_size = RTC_SRAM_SIZE;
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ret = ds3232_rtc_read8(dev, RTC_STAT_REG_ADDR);
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if (ret < 0)
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return ret;
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rtc_status = ret;
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ret = verify_osc(dev);
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if (ret < 0)
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return ret;
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rtc_status &= ~(RTC_STAT_BIT_OSF | RTC_STAT_BIT_A1F | RTC_STAT_BIT_A2F);
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return ds3232_rtc_write8(dev, RTC_STAT_REG_ADDR, rtc_status);
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}
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static const struct rtc_ops ds3232_rtc_ops = {
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.get = ds3232_rtc_get,
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.set = ds3232_rtc_set,
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.reset = ds3232_rtc_reset,
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.read8 = ds3232_rtc_read8,
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.write8 = ds3232_rtc_write8
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};
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static const struct udevice_id ds3232_rtc_ids[] = {
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{ .compatible = "dallas,ds3232" },
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{ }
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};
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U_BOOT_DRIVER(rtc_ds3232) = {
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.name = "rtc-ds3232",
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.id = UCLASS_RTC,
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.probe = ds3232_probe,
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.of_match = ds3232_rtc_ids,
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.ops = &ds3232_rtc_ops,
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.priv_auto = sizeof(struct ds3232_priv_data),
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};
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