89 lines
2.9 KiB
C
89 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* From Coreboot file of same name
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*/
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#ifndef _ASM_SPEEDSTEP_H
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#define _ASM_SPEEDSTEP_H
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/* Magic value used to locate speedstep configuration in the device tree */
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#define SPEEDSTEP_APIC_MAGIC 0xACAC
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/* MWAIT coordination I/O base address. This must match
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* the \_PR_.CPU0 PM base address.
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*/
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#define PMB0_BASE 0x510
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/* PMB1: I/O port that triggers SMI once cores are in the same state.
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* See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
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*/
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#define PMB1_BASE 0x800
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struct sst_state {
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uint8_t dynfsb:1; /* whether this is SLFM */
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uint8_t nonint:1; /* add .5 to ratio */
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uint8_t ratio:6;
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uint8_t vid;
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uint8_t is_turbo;
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uint8_t is_slfm;
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uint32_t power;
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};
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#define SPEEDSTEP_RATIO_SHIFT 8
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#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT)
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#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
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#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT)
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#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
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#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT)
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#define SPEEDSTEP_VID_MASK 0x3f
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#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \
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0, /* dynfsb won't be read. */ \
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((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
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(((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
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>> SPEEDSTEP_RATIO_SHIFT), \
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(val & mask) & SPEEDSTEP_VID_MASK, \
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0, /* not turbo by default */ \
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0, /* not slfm by default */ \
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0 /* power is hardcoded in software. */ \
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})
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#define SPEEDSTEP_ENCODE_STATE(state) ( \
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((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
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((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
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((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
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((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
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#define SPEEDSTEP_DOUBLE_RATIO(state) ( \
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((uint8_t)(state).ratio * 2) + (state).nonint)
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struct sst_params {
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struct sst_state slfm;
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struct sst_state min;
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struct sst_state max;
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struct sst_state turbo;
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};
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/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
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processor is 14, the lowest is always 6. This makes 5 states with the
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minimal step width of 2. With turbo mode and super LFM we have at most 7. */
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#define SPEEDSTEP_MAX_NORMAL_STATES 5
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#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2)
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struct sst_table {
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/* Table of p-states for EMTTM and ACPI by decreasing performance. */
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struct sst_state states[SPEEDSTEP_MAX_STATES];
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int num_states;
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};
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void speedstep_gen_pstates(struct sst_table *);
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#define SPEEDSTEP_MAX_POWER_YONAH 31000
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#define SPEEDSTEP_MIN_POWER_YONAH 13100
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#define SPEEDSTEP_MAX_POWER_MEROM 35000
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#define SPEEDSTEP_MIN_POWER_MEROM 25000
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#define SPEEDSTEP_SLFM_POWER_MEROM 12000
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#define SPEEDSTEP_MAX_POWER_PENRYN 35000
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#define SPEEDSTEP_MIN_POWER_PENRYN 15000
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#define SPEEDSTEP_SLFM_POWER_PENRYN 12000
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#endif
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