209 lines
6.1 KiB
C
209 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <contact@8051projects.net>
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*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*/
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#ifndef __ARMADA100_FEC_H__
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#define __ARMADA100_FEC_H__
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#define PORT_NUM 0x0
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/* RX & TX descriptor command */
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#define BUF_OWNED_BY_DMA (1<<31)
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/* RX descriptor status */
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#define RX_EN_INT (1<<23)
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#define RX_FIRST_DESC (1<<17)
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#define RX_LAST_DESC (1<<16)
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#define RX_ERROR (1<<15)
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/* TX descriptor command */
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#define TX_EN_INT (1<<23)
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#define TX_GEN_CRC (1<<22)
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#define TX_ZERO_PADDING (1<<18)
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#define TX_FIRST_DESC (1<<17)
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#define TX_LAST_DESC (1<<16)
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#define TX_ERROR (1<<15)
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/* smi register */
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#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */
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#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */
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#define SMI_OP_W (0<<26) /* Write operation */
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#define SMI_OP_R (1<<26) /* Read operation */
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#define HASH_ADD 0
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#define HASH_DELETE 1
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#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
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#define HOP_NUMBER 12
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#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
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#define PHY_WAIT_MICRO_SECONDS 10
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#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
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#define ETH_EXTRA_HEADER (6+6+2+4)
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/* dest+src addr+protocol id+crc */
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#define MAX_PKT_SIZE 1536
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/* Bit definitions of the SDMA Config Reg */
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#define SDCR_BSZ_OFF 12
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#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF)
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#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF)
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#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF)
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#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF)
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#define SDCR_BLMR (1<<6)
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#define SDCR_BLMT (1<<7)
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#define SDCR_RIFB (1<<9)
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#define SDCR_RC_OFF 2
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#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
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/* SDMA_CMD */
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#define SDMA_CMD_AT (1<<31)
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#define SDMA_CMD_TXDL (1<<24)
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#define SDMA_CMD_TXDH (1<<23)
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#define SDMA_CMD_AR (1<<15)
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#define SDMA_CMD_ERD (1<<7)
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/* Bit definitions of the Port Config Reg */
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#define PCR_HS (1<<12)
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#define PCR_EN (1<<7)
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#define PCR_PM (1<<0)
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/* Bit definitions of the Port Config Extend Reg */
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#define PCXR_2BSM (1<<28)
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#define PCXR_DSCP_EN (1<<21)
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#define PCXR_MFL_1518 (0<<14)
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#define PCXR_MFL_1536 (1<<14)
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#define PCXR_MFL_2048 (2<<14)
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#define PCXR_MFL_64K (3<<14)
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#define PCXR_FLP (1<<11)
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#define PCXR_PRIO_TX_OFF 3
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#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF)
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/*
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* * Bit definitions of the Interrupt Cause Reg
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* * and Interrupt MASK Reg is the same
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* */
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#define ICR_RXBUF (1<<0)
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#define ICR_TXBUF_H (1<<2)
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#define ICR_TXBUF_L (1<<3)
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#define ICR_TXEND_H (1<<6)
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#define ICR_TXEND_L (1<<7)
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#define ICR_RXERR (1<<8)
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#define ICR_TXERR_H (1<<10)
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#define ICR_TXERR_L (1<<11)
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#define ICR_TX_UDR (1<<13)
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#define ICR_MII_CH (1<<28)
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#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
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ICR_TXERR_H | ICR_TXERR_L |\
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ICR_TXEND_H | ICR_TXEND_L |\
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ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
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#define PHY_MASK 0x0000001f
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#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
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/* Size of a Tx/Rx descriptor used in chain list data structure */
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#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
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(((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
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#define RX_BUF_OFFSET 0x2
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#define RXQ 0x0 /* RX Queue 0 */
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#define TXQ 0x1 /* TX Queue 1 */
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struct addr_table_entry_t {
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u32 lo;
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u32 hi;
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};
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/* Bit fields of a Hash Table Entry */
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enum hash_table_entry {
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HTEVALID = 1,
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HTESKIP = 2,
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HTERD = 4,
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HTERDBIT = 2
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};
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struct tx_desc {
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u32 cmd_sts; /* Command/status field */
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u16 reserved;
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u16 byte_cnt; /* buffer byte count */
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u8 *buf_ptr; /* pointer to buffer for this descriptor */
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struct tx_desc *nextdesc_p; /* Pointer to next descriptor */
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};
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struct rx_desc {
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u32 cmd_sts; /* Descriptor command status */
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u16 byte_cnt; /* Descriptor buffer byte count */
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u16 buf_size; /* Buffer size */
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u8 *buf_ptr; /* Descriptor buffer pointer */
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struct rx_desc *nxtdesc_p; /* Next descriptor pointer */
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};
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/*
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* Armada100 Fast Ethernet controller Registers
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* Refer Datasheet Appendix A.22
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*/
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struct armdfec_reg {
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u32 phyadr; /* PHY Address */
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u32 pad1[3];
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u32 smi; /* SMI */
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u32 pad2[0xFB];
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u32 pconf; /* Port configuration */
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u32 pad3;
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u32 pconf_ext; /* Port configuration extend */
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u32 pad4;
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u32 pcmd; /* Port Command */
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u32 pad5;
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u32 pstatus; /* Port Status */
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u32 pad6;
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u32 spar; /* Serial Parameters */
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u32 pad7;
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u32 htpr; /* Hash table pointer */
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u32 pad8;
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u32 fcsal; /* Flow control source address low */
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u32 pad9;
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u32 fcsah; /* Flow control source address high */
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u32 pad10;
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u32 sdma_conf; /* SDMA configuration */
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u32 pad11;
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u32 sdma_cmd; /* SDMA command */
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u32 pad12;
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u32 ic; /* Interrupt cause */
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u32 iwc; /* Interrupt write to clear */
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u32 im; /* Interrupt mask */
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u32 pad13;
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u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
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Point to Priority 0 Low */
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u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
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u32 pad14[3];
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struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor
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Pointer */
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u32 pad15[4];
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struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor
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Pointer */
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u32 pad16[0x0C];
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struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor
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Pointer */
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};
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struct armdfec_device {
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struct eth_device dev;
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struct armdfec_reg *regs;
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struct tx_desc *p_txdesc;
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struct rx_desc *p_rxdesc;
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struct rx_desc *p_rxdesc_curr;
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u8 *p_rxbuf;
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u8 *p_aligned_txbuf;
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u8 *htpr; /* hash pointer */
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};
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#endif /* __ARMADA100_FEC_H__ */
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