Brad Kim fb33eaa3a2 riscv: fix the wrong swap value register ... Not s2 register, t1 register is correct Fortunately, it works because t1 register has a garbage value Signed-off-by: Brad Kim <brad.kim@semifive.com> Reviewed-by: Lukas Auer <lukas@auer.io> Reviewed-by: Leo Liang <ycliang@andestech.com>		2020-12-14 15:16:34 +08:00
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ax25	timer: Add _TIMER suffix to Andes PLMT Kconfig	2020-10-26 10:01:28 +08:00
fu540	riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller	2020-11-28 08:30:41 +01:00
generic	riscv: Rework riscv timer driver to only support S-mode	2020-09-30 08:54:45 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
cpu.c	riscv: Clear pending IPIs on initialization	2020-09-30 08:54:52 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: fix the wrong swap value register	2020-12-14 15:16:34 +08:00
u-boot-spl.lds	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00