230 lines
6.2 KiB
C
230 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* ENETC ethernet controller driver
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* Copyright 2017-2019 NXP
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*/
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#ifndef _ENETC_H
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#define _ENETC_H
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#define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
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/* PCI function IDs */
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#define PCI_DEVICE_ID_ENETC_ETH 0xE100
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#define PCI_DEVICE_ID_ENETC_MDIO 0xEE01
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/* ENETC Ethernet controller registers */
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/* Station interface register offsets */
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#define ENETC_SIMR 0x000
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#define ENETC_SIMR_EN BIT(31)
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#define ENETC_SICAR0 0x040
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/* write cache cfg: snoop, no allocate, data & BD coherent */
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#define ENETC_SICAR_WR_CFG 0x6767
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/* read cache cfg: coherent copy, look up, don't alloc in cache */
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#define ENETC_SICAR_RD_CFG 0x27270000
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#define ENETC_SIROCT 0x300
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#define ENETC_SIRFRM 0x308
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#define ENETC_SITOCT 0x320
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#define ENETC_SITFRM 0x328
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/* Rx/Tx Buffer Descriptor Ring registers */
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enum enetc_bdr_type {TX, RX};
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#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
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#define ENETC_BDR_IDX_MASK 0xffff
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/* Rx BDR reg offsets */
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#define ENETC_RBMR 0x00
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#define ENETC_RBMR_EN BIT(31)
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#define ENETC_RBBSR 0x08
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/* initial consumer index for Rx BDR */
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#define ENETC_RBCIR 0x0c
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#define ENETC_RBBAR0 0x10
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#define ENETC_RBBAR1 0x14
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#define ENETC_RBPIR 0x18
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#define ENETC_RBLENR 0x20
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/* Tx BDR reg offsets */
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#define ENETC_TBMR 0x00
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#define ENETC_TBMR_EN BIT(31)
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#define ENETC_TBBAR0 0x10
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#define ENETC_TBBAR1 0x14
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#define ENETC_TBPIR 0x18
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#define ENETC_TBCIR 0x1c
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#define ENETC_TBLENR 0x20
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/* Port registers offset */
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#define ENETC_PORT_REGS_OFF 0x10000
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/* Port registers */
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#define ENETC_PMR 0x0000
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#define ENETC_PMR_SI0_EN BIT(16)
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#define ENETC_PSIPMMR 0x0018
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#define ENETC_PSIPMAR0 0x0100
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#define ENETC_PSIPMAR1 0x0104
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#define ENETC_PCAPR0 0x0900
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#define ENETC_PCAPRO_MDIO BIT(11)
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#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
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#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
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#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
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/* MAC configuration */
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#define ENETC_PM_CC 0x8008
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#define ENETC_PM_CC_DEFAULT 0x0810
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#define ENETC_PM_CC_RX_TX_EN 0x8813
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#define ENETC_PM_MAXFRM 0x8014
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#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
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#define ENETC_PM_IMDIO_BASE 0x8030
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#define ENETC_PM_IF_MODE 0x8300
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#define ENETC_PM_IF_MODE_RG BIT(2)
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#define ENETC_PM_IF_MODE_AN_ENA BIT(15)
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#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
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/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
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#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
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#define ENETC_BD_ALIGN 128
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/* single pair of Rx/Tx rings */
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#define ENETC_RX_BDR_CNT 1
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#define ENETC_TX_BDR_CNT 1
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#define ENETC_RX_BDR_ID 0
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#define ENETC_TX_BDR_ID 0
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/* Tx buffer descriptor */
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struct enetc_tx_bd {
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__le64 addr;
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__le16 buf_len;
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__le16 frm_len;
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__le16 err_csum;
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__le16 flags;
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};
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#define ENETC_TXBD_FLAGS_F BIT(15)
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#define ENETC_POLL_TRIES 32000
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/* Rx buffer descriptor */
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union enetc_rx_bd {
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/* SW provided BD format */
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struct {
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__le64 addr;
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u8 reserved[8];
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} w;
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/* ENETC returned BD format */
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struct {
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__le16 inet_csum;
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__le16 parse_summary;
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__le32 rss_hash;
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__le16 buf_len;
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__le16 vlan_opt;
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union {
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struct {
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__le16 flags;
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__le16 error;
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};
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__le32 lstatus;
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};
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} r;
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};
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#define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
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#define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
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#define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
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#define ENETC_RXBD_STATUS(flags) ((flags) << 16)
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/* Tx/Rx ring info */
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struct bd_ring {
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void *cons_idx;
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void *prod_idx;
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/* next BD index to use */
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int next_prod_idx;
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int next_cons_idx;
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int bd_count;
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};
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/* ENETC private structure */
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struct enetc_priv {
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struct enetc_tx_bd *enetc_txbd;
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union enetc_rx_bd *enetc_rxbd;
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void *regs_base; /* base ENETC registers */
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void *port_regs; /* base ENETC port registers */
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/* Rx/Tx buffer descriptor rings info */
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struct bd_ring tx_bdr;
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struct bd_ring rx_bdr;
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int if_type;
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struct mii_dev imdio;
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};
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/* register accessors */
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#define enetc_read_reg(x) readl((x))
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#define enetc_write_reg(x, val) writel((val), (x))
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#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
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#define enetc_write(priv, off, v) \
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enetc_write_reg((priv)->regs_base + (off), v)
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/* port register accessors */
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#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
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#define enetc_read_port(priv, off) \
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enetc_read_reg(enetc_port_regs((priv), (off)))
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#define enetc_write_port(priv, off, v) \
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enetc_write_reg(enetc_port_regs((priv), (off)), v)
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/* BDR register accessors, see ENETC_BDR() */
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#define enetc_bdr_read(priv, t, n, off) \
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enetc_read(priv, ENETC_BDR(t, n, off))
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#define enetc_bdr_write(priv, t, n, off, val) \
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enetc_write(priv, ENETC_BDR(t, n, off), val)
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/* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
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#define ENETC_PCS_PHY_ADDR 0
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/* PCS registers */
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#define ENETC_PCS_CR 0x00
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#define ENETC_PCS_CR_RESET_AN 0x1200
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#define ENETC_PCS_CR_DEF_VAL 0x0140
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#define ENETC_PCS_CR_RST BIT(15)
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#define ENETC_PCS_DEV_ABILITY 0x04
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#define ENETC_PCS_DEV_ABILITY_SGMII 0x4001
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#define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001
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#define ENETC_PCS_LINK_TIMER1 0x12
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#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
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#define ENETC_PCS_LINK_TIMER2 0x13
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#define ENETC_PCS_LINK_TIMER2_VAL 0x0003
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#define ENETC_PCS_IF_MODE 0x14
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#define ENETC_PCS_IF_MODE_SGMII BIT(0)
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#define ENETC_PCS_IF_MODE_SGMII_AN BIT(1)
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#define ENETC_PCS_IF_MODE_SPEED_1G BIT(3)
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/* PCS replicator block for USXGMII */
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#define ENETC_PCS_DEVAD_REPL 0x1f
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/* ENETC external MDIO registers */
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#define ENETC_MDIO_BASE 0x1c00
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#define ENETC_MDIO_CFG 0x00
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#define ENETC_EMDIO_CFG_C22 0x00809508
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#define ENETC_EMDIO_CFG_C45 0x00809548
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#define ENETC_EMDIO_CFG_RD_ER BIT(1)
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#define ENETC_EMDIO_CFG_BSY BIT(0)
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#define ENETC_MDIO_CTL 0x04
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#define ENETC_MDIO_CTL_READ BIT(15)
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#define ENETC_MDIO_DATA 0x08
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#define ENETC_MDIO_STAT 0x0c
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#define ENETC_MDIO_READ_ERR 0xffff
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struct enetc_mdio_priv {
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void *regs_base;
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};
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/*
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* these functions are implemented by ENETC_MDIO and are re-used by ENETC driver
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* to drive serdes / internal SoC PHYs
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*/
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int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
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int reg);
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int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
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int reg, u16 val);
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#endif /* _ENETC_H */
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