263 lines
6.3 KiB
C
263 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SAMSUNG EXYNOS USB HOST EHCI Controller
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*
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* Copyright (C) 2012 Samsung Electronics Co.Ltd
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* Vivek Gautam <gautam.vivek@samsung.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <usb.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ehci.h>
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#include <asm/arch/system.h>
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#include <asm/arch/power.h>
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#include <asm/gpio.h>
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#include <linux/errno.h>
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#include <linux/compat.h>
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#include "ehci.h"
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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struct exynos_ehci_platdata {
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struct usb_platdata usb_plat;
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fdt_addr_t hcd_base;
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fdt_addr_t phy_base;
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struct gpio_desc vbus_gpio;
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};
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/**
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* Contains pointers to register base addresses
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* for the usb controller.
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*/
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struct exynos_ehci {
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struct ehci_ctrl ctrl;
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struct exynos_usb_phy *usb;
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struct ehci_hccr *hcd;
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};
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static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
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{
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struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
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const void *blob = gd->fdt_blob;
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unsigned int node;
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int depth;
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/*
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* Get the base address for XHCI controller from the device node
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*/
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plat->hcd_base = devfdt_get_addr(dev);
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if (plat->hcd_base == FDT_ADDR_T_NONE) {
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debug("Can't get the XHCI register base address\n");
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return -ENXIO;
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}
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depth = 0;
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node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
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COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
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if (node <= 0) {
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debug("XHCI: Can't get device node for usb3-phy controller\n");
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return -ENODEV;
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}
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/*
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* Get the base address for usbphy from the device node
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*/
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plat->phy_base = fdtdec_get_addr(blob, node, "reg");
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if (plat->phy_base == FDT_ADDR_T_NONE) {
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debug("Can't get the usbphy register address\n");
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return -ENXIO;
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}
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/* Vbus gpio */
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gpio_request_by_name(dev, "samsung,vbus-gpio", 0,
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&plat->vbus_gpio, GPIOD_IS_OUT);
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return 0;
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}
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static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
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{
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u32 hsic_ctrl;
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clrbits_le32(&usb->usbphyctrl0,
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HOST_CTRL0_FSEL_MASK |
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HOST_CTRL0_COMMONON_N |
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/* HOST Phy setting */
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HOST_CTRL0_PHYSWRST |
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HOST_CTRL0_PHYSWRSTALL |
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HOST_CTRL0_SIDDQ |
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HOST_CTRL0_FORCESUSPEND |
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HOST_CTRL0_FORCESLEEP);
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setbits_le32(&usb->usbphyctrl0,
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/* Setting up the ref freq */
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(CLK_24MHZ << 16) |
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/* HOST Phy setting */
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HOST_CTRL0_LINKSWRST |
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HOST_CTRL0_UTMISWRST);
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udelay(10);
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clrbits_le32(&usb->usbphyctrl0,
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HOST_CTRL0_LINKSWRST |
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HOST_CTRL0_UTMISWRST);
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/* HSIC Phy Setting */
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hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
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HSIC_CTRL_FORCESLEEP |
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HSIC_CTRL_SIDDQ);
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clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
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clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
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hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
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<< HSIC_CTRL_REFCLKDIV_SHIFT)
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| ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
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<< HSIC_CTRL_REFCLKSEL_SHIFT)
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| HSIC_CTRL_UTMISWRST);
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setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
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setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
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udelay(10);
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clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
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HSIC_CTRL_UTMISWRST);
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clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
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HSIC_CTRL_UTMISWRST);
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udelay(20);
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/* EHCI Ctrl setting */
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setbits_le32(&usb->ehcictrl,
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EHCICTRL_ENAINCRXALIGN |
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EHCICTRL_ENAINCR4 |
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EHCICTRL_ENAINCR8 |
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EHCICTRL_ENAINCR16);
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}
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static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
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{
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writel(CLK_24MHZ, &usb->usbphyclk);
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clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
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PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
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PHYPWR_NORMAL_MASK_PHY0));
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setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
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udelay(10);
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clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
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}
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static void setup_usb_phy(struct exynos_usb_phy *usb)
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{
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set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
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set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
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if (cpu_is_exynos5())
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exynos5_setup_usb_phy(usb);
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else if (cpu_is_exynos4())
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if (proid_is_exynos4412())
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exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
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usb);
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}
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static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
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{
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u32 hsic_ctrl;
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/* HOST_PHY reset */
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setbits_le32(&usb->usbphyctrl0,
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HOST_CTRL0_PHYSWRST |
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HOST_CTRL0_PHYSWRSTALL |
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HOST_CTRL0_SIDDQ |
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HOST_CTRL0_FORCESUSPEND |
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HOST_CTRL0_FORCESLEEP);
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/* HSIC Phy reset */
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hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
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HSIC_CTRL_FORCESLEEP |
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HSIC_CTRL_SIDDQ |
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HSIC_CTRL_PHYSWRST);
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setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
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setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
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}
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static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
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{
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setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
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PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
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PHYPWR_NORMAL_MASK_PHY0));
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}
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/* Reset the EHCI host controller. */
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static void reset_usb_phy(struct exynos_usb_phy *usb)
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{
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if (cpu_is_exynos5())
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exynos5_reset_usb_phy(usb);
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else if (cpu_is_exynos4())
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if (proid_is_exynos4412())
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exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
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usb);
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set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
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}
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static int ehci_usb_probe(struct udevice *dev)
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{
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struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
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struct exynos_ehci *ctx = dev_get_priv(dev);
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struct ehci_hcor *hcor;
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ctx->hcd = (struct ehci_hccr *)plat->hcd_base;
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ctx->usb = (struct exynos_usb_phy *)plat->phy_base;
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/* setup the Vbus gpio here */
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if (dm_gpio_is_valid(&plat->vbus_gpio))
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dm_gpio_set_value(&plat->vbus_gpio, 1);
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setup_usb_phy(ctx->usb);
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hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd +
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HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase)));
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return ehci_register(dev, ctx->hcd, hcor, NULL, 0, USB_INIT_HOST);
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}
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static int ehci_usb_remove(struct udevice *dev)
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{
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struct exynos_ehci *ctx = dev_get_priv(dev);
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int ret;
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ret = ehci_deregister(dev);
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if (ret)
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return ret;
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reset_usb_phy(ctx->usb);
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return 0;
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}
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static const struct udevice_id ehci_usb_ids[] = {
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{ .compatible = "samsung,exynos-ehci" },
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{ }
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};
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U_BOOT_DRIVER(usb_ehci) = {
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.name = "ehci_exynos",
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.id = UCLASS_USB,
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.of_match = ehci_usb_ids,
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.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
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.probe = ehci_usb_probe,
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.remove = ehci_usb_remove,
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.ops = &ehci_usb_ops,
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.priv_auto_alloc_size = sizeof(struct exynos_ehci),
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.platdata_auto_alloc_size = sizeof(struct exynos_ehci_platdata),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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