227 lines
6.1 KiB
C
227 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*/
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#include <dm.h>
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#include <fdt_support.h>
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#include <log.h>
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#include <miiphy.h>
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#include <net.h>
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#include <linux/delay.h>
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#include <mach/cvmx-regs.h>
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#include <mach/cvmx-csr.h>
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#include <mach/octeon-model.h>
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#include <mach/octeon-feature.h>
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#include <mach/cvmx-smix-defs.h>
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#include <mach/cvmx-config.h>
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#include <mach/cvmx-helper.h>
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#include <mach/cvmx-helper-board.h>
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#include <mach/cvmx-mdio.h>
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#define CVMX_SMI_DRV_CTL 0x0001180000001828ull
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#define DEFAULT_MDIO_SPEED 2500000 /** 2.5 MHz default speed */
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/**
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* cvmx_smi_drv_ctl
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*
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* Enables the SMI interface.
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*
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*/
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union cvmx_smi_drv_ctl {
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u64 u64;
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struct cvmx_smi_drv_ctl_s {
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u64 reserved_14_63 : 50;
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u64 pctl : 6;
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u64 reserved_6_7 : 2;
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u64 nctl : 6;
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} s;
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};
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struct octeon_mdiobus {
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struct mii_dev *mii_dev;
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/**
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* The local bus is in the lower 8 bits, followed by the remote bus in
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* the top 8 bits. Bit 16 will be set if the bus is non-local.
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*/
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u32 bus_id;
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int node; /** Node number */
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int speed; /** Bus speed, normally 2.5 MHz */
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int fdt_node; /** Node in FDT */
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bool local; /** true if local MDIO bus */
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};
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static int octeon_mdio_read(struct udevice *mdio_dev, int phy_addr,
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int dev_addr, int reg_addr)
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{
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struct octeon_mdiobus *p = dev_get_priv(mdio_dev);
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struct mii_dev *dev = p->mii_dev;
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int value;
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debug("%s(0x%p(%s): bus_id=%d phy_addr=%d, 0x%x, 0x%x) - ", __func__,
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dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr);
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if (IS_ENABLED(CONFIG_PHYLIB_10G) && dev_addr != MDIO_DEVAD_NONE) {
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debug("clause 45 mode\n");
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value = cvmx_mdio_45_read(p->bus_id & 0xff, phy_addr, dev_addr,
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reg_addr);
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} else {
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value = cvmx_mdio_read(p->bus_id & 0xff, phy_addr, reg_addr);
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}
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debug("Return value: 0x%x\n", value);
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return value;
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}
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static int octeon_mdio_write(struct udevice *mdio_dev, int phy_addr,
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int dev_addr, int reg_addr, u16 value)
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{
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struct octeon_mdiobus *p = dev_get_priv(mdio_dev);
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struct mii_dev *dev = p->mii_dev;
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debug("%s(0x%p(%s): bus_id=%d phy_addr=%d, 0x%x, 0x%x, 0x%x)\n",
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__func__, dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr,
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value);
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if (IS_ENABLED(CONFIG_PHYLIB_10G) && dev_addr != MDIO_DEVAD_NONE) {
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debug("clause 45 mode\n");
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return cvmx_mdio_45_write(p->bus_id & 0xff, phy_addr, dev_addr,
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reg_addr, value);
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}
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return cvmx_mdio_write(p->bus_id & 0xff, phy_addr, reg_addr, value);
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}
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/**
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* Converts a MDIO register address to a bus number
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*
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* @param reg_addr MDIO base register address
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*
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* @return MDIO bus number or -1 if invalid address
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*/
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int octeon_mdio_reg_addr_to_bus(u64 reg_addr)
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{
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int bus_base;
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int bus;
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/* Adjust the bus number based on the node number */
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bus_base = cvmx_csr_addr_to_node(reg_addr) * 4;
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reg_addr = cvmx_csr_addr_strip_node(reg_addr);
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switch (reg_addr) {
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case 0x1180000001800:
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case 0x1180000003800: /* 68XX/78XX address */
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bus = 0;
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break;
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case 0x1180000001900:
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case 0x1180000003880:
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bus = 1;
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break;
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case 0x1180000003900:
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bus = 2;
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break;
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case 0x1180000003980:
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bus = 3;
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break;
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default:
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printf("%s: Unknown register address 0x%llx\n", __func__,
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reg_addr);
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return -1;
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}
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bus += bus_base;
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debug("%s: address 0x%llx is bus %d\n", __func__, reg_addr, bus);
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return bus;
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}
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static int octeon_mdio_probe(struct udevice *dev)
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{
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struct octeon_mdiobus *p = dev_get_priv(dev);
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union cvmx_smi_drv_ctl drv_ctl;
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cvmx_smix_clk_t smi_clk;
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u64 mdio_addr;
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int bus;
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u64 sclock;
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u32 sample_dly;
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u64 denom;
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mdio_addr = dev_read_addr(dev);
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debug("%s: Translated address: 0x%llx\n", __func__, mdio_addr);
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bus = octeon_mdio_reg_addr_to_bus(mdio_addr);
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p->bus_id = bus;
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debug("%s: bus: %d\n", __func__, bus);
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drv_ctl.u64 = csr_rd(CVMX_SMI_DRV_CTL);
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drv_ctl.s.pctl = dev_read_u32_default(dev, "cavium,pctl-drive-strength",
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drv_ctl.s.pctl);
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drv_ctl.s.nctl = dev_read_u32_default(dev, "cavium,nctl-drive-strength",
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drv_ctl.s.nctl);
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debug("%s: Set MDIO PCTL drive strength to 0x%x and NCTL drive strength to 0x%x\n",
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__func__, drv_ctl.s.pctl, drv_ctl.s.nctl);
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csr_wr(CVMX_SMI_DRV_CTL, drv_ctl.u64);
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/* Set the bus speed, default is 2.5MHz */
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p->speed = dev_read_u32_default(dev, "cavium,max-speed",
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DEFAULT_MDIO_SPEED);
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sclock = gd->bus_clk;
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smi_clk.u64 = csr_rd(CVMX_SMIX_CLK(bus & 3));
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smi_clk.s.phase = sclock / (p->speed * 2);
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/* Allow sample delay to be specified */
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sample_dly = dev_read_u32_default(dev, "cavium,sample-delay", 0);
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/* Only change the sample delay if it is set, otherwise use
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* the default value of 2.
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*/
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if (sample_dly) {
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u32 sample;
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denom = (sclock * 1000ULL) / sample_dly;
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debug("%s: sclock: %llu, sample_dly: %u ps, denom: %llu\n",
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__func__, sclock, sample_dly, denom);
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sample = (sclock + denom - 1) / denom;
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debug("%s: sample: %u\n", __func__, smi_clk.s.sample);
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if (sample < 2) {
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printf("%s: warning: cavium,sample-delay %u ps is too small in device tree for %s\n",
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__func__, sample_dly, dev->name);
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sample = 2;
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}
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if (sample > (2 * smi_clk.s.phase - 3)) {
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printf("%s: warning: cavium,sample-delay %u ps is too large in device tree for %s\n",
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__func__, sample_dly, dev->name);
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sample = 2 * smi_clk.s.phase - 3;
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}
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smi_clk.s.sample = sample & 0xf;
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smi_clk.s.sample_hi = (sample >> 4) & 0xf;
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debug("%s(%s): sample delay: %u ps (%d clocks)\n", __func__,
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dev->name, sample_dly, smi_clk.s.sample);
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}
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csr_wr(CVMX_SMIX_CLK(bus & 3), smi_clk.u64);
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debug("mdio clock phase: %d clocks\n", smi_clk.s.phase);
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csr_wr(CVMX_SMIX_CLK(bus & 3), smi_clk.u64);
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debug("Enabling SMI interface %s\n", dev->name);
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csr_wr(CVMX_SMIX_EN(bus & 3), 1);
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/* Muxed MDIO bus support removed for now! */
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return 0;
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}
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static const struct mdio_ops octeon_mdio_ops = {
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.read = octeon_mdio_read,
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.write = octeon_mdio_write,
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};
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static const struct udevice_id octeon_mdio_ids[] = {
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{ .compatible = "cavium,octeon-3860-mdio" },
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{}
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};
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U_BOOT_DRIVER(octeon_mdio) = {
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.name = "octeon_mdio",
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.id = UCLASS_MDIO,
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.of_match = octeon_mdio_ids,
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.probe = octeon_mdio_probe,
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.ops = &octeon_mdio_ops,
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.priv_auto = sizeof(struct octeon_mdiobus),
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};
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