123 lines
2.6 KiB
C
123 lines
2.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi SoCs pinctrl driver
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*
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* Author: <gregory.clement@bootlin.com>
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* License: Dual MIT/GPL
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm-generic/gpio.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <errno.h>
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enum {
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SDI,
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CS0,
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CS1,
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CS2,
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CS3,
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SDO,
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SCK
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};
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static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
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#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
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#define SW_SPI_CS0_OE BIT(1)
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#define SW_SPI_SDO_OE BIT(9)
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#define SW_SPI_SCK_OE BIT(11)
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#define SW_PIN_CTRL_MODE BIT(13)
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struct mscc_bb_spi_gpio {
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void __iomem *regs;
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u32 cache_val;
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};
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static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
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{
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struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
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if (val)
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gpio->cache_val |= BIT(pinmap[oft]);
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else
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gpio->cache_val &= ~BIT(pinmap[oft]);
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writel(gpio->cache_val, gpio->regs);
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return 0;
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}
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static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
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int val)
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{
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if (oft == 0) {
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pr_err("SW_SPI_DSI can't be used as output\n");
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return -ENOTSUPP;
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}
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mscc_bb_spi_gpio_set(dev, oft, val);
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return 0;
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}
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static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
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{
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return 0;
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}
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static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
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{
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struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
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u32 val = readl(gpio->regs);
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return !!(val & BIT(pinmap[oft]));
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}
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static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
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.direction_output = mscc_bb_spi_gpio_direction_output,
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.direction_input = mscc_bb_spi_gpio_direction_input,
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.set_value = mscc_bb_spi_gpio_set,
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.get_value = mscc_bb_spi_gpio_get,
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};
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static int mscc_bb_spi_gpio_probe(struct udevice *dev)
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{
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struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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gpio->regs = dev_remap_addr(dev);
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if (!gpio->regs)
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return -EINVAL;
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uc_priv->bank_name = dev->name;
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uc_priv->gpio_count = ARRAY_SIZE(pinmap);
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/*
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* Enable software mode to control the SPI pin, enables the
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* output mode for most of the pin and initialize the cache
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* value in the same time
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*/
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gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
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SW_SPI_CS0_OE;
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writel(gpio->cache_val, gpio->regs);
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return 0;
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}
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static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
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{.compatible = "mscc,spi-bitbang-gpio"},
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{}
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};
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U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
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.name = "gpio-mscc-spi-bitbang",
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.id = UCLASS_GPIO,
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.ops = &mscc_bb_spi_gpio_ops,
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.probe = mscc_bb_spi_gpio_probe,
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.of_match = of_match_ptr(mscc_bb_spi_gpio_ids),
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.priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio),
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};
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