136 lines
3.1 KiB
C
136 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Actions Semi OWL SoCs UART driver
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*
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* Copyright (C) 2015 Actions Semi Co., Ltd.
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* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <asm/types.h>
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/* UART Registers */
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#define OWL_UART_CTL (0x0000)
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#define OWL_UART_RXDAT (0x0004)
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#define OWL_UART_TXDAT (0x0008)
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#define OWL_UART_STAT (0x000C)
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/* UART_CTL Register Definitions */
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#define OWL_UART_CTL_PRS_NONE GENMASK(6, 4)
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#define OWL_UART_CTL_STPS BIT(2)
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#define OWL_UART_CTL_DWLS 3
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/* UART_STAT Register Definitions */
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#define OWL_UART_STAT_TFES BIT(10) /* TX FIFO Empty Status */
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#define OWL_UART_STAT_RFFS BIT(9) /* RX FIFO full Status */
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#define OWL_UART_STAT_TFFU BIT(6) /* TX FIFO full Status */
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#define OWL_UART_STAT_RFEM BIT(5) /* RX FIFO Empty Status */
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struct owl_serial_priv {
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phys_addr_t base;
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};
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int owl_serial_setbrg(struct udevice *dev, int baudrate)
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{
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/* Driver supports only fixed baudrate */
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return 0;
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}
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static int owl_serial_getc(struct udevice *dev)
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{
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struct owl_serial_priv *priv = dev_get_priv(dev);
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if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_RFEM)
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return -EAGAIN;
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return (int)(readl(priv->base + OWL_UART_RXDAT));
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}
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static int owl_serial_putc(struct udevice *dev, const char ch)
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{
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struct owl_serial_priv *priv = dev_get_priv(dev);
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if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_TFFU)
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return -EAGAIN;
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writel(ch, priv->base + OWL_UART_TXDAT);
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return 0;
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}
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static int owl_serial_pending(struct udevice *dev, bool input)
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{
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struct owl_serial_priv *priv = dev_get_priv(dev);
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unsigned int stat = readl(priv->base + OWL_UART_STAT);
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if (input)
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return !(stat & OWL_UART_STAT_RFEM);
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else
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return !(stat & OWL_UART_STAT_TFES);
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}
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static int owl_serial_probe(struct udevice *dev)
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{
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struct owl_serial_priv *priv = dev_get_priv(dev);
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struct clk clk;
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u32 uart_ctl;
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int ret;
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/* Set data, parity and stop bits */
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uart_ctl = readl(priv->base + OWL_UART_CTL);
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uart_ctl &= ~(OWL_UART_CTL_PRS_NONE);
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uart_ctl &= ~(OWL_UART_CTL_STPS);
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uart_ctl |= OWL_UART_CTL_DWLS;
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writel(uart_ctl, priv->base + OWL_UART_CTL);
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/* Enable UART clock */
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int owl_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct owl_serial_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct dm_serial_ops owl_serial_ops = {
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.putc = owl_serial_putc,
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.pending = owl_serial_pending,
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.getc = owl_serial_getc,
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.setbrg = owl_serial_setbrg,
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};
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static const struct udevice_id owl_serial_ids[] = {
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{ .compatible = "actions,s900-serial" },
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{ }
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};
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U_BOOT_DRIVER(serial_owl) = {
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.name = "serial_owl",
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.id = UCLASS_SERIAL,
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.of_match = owl_serial_ids,
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.ofdata_to_platdata = owl_serial_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct owl_serial_priv),
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.probe = owl_serial_probe,
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.ops = &owl_serial_ops,
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};
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