172 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			172 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
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|  */
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| 
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| #include <common.h>
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| #include <dm.h>
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| #include <dm/ofnode.h>
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| #include <mapmem.h>
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| #include <asm/arch/timer.h>
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| #include <dt-structs.h>
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| #include <timer.h>
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| #include <asm/io.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| #if CONFIG_IS_ENABLED(OF_PLATDATA)
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| struct rockchip_timer_plat {
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| 	struct dtd_rockchip_rk3368_timer dtd;
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| };
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| #endif
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| 
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| /* Driver private data. Contains timer id. Could be either 0 or 1. */
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| struct rockchip_timer_priv {
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| 	struct rk_timer *timer;
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| };
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| 
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| static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
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| {
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| 	uint64_t timebase_h, timebase_l;
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| 	uint64_t cntr;
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| 
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| 	timebase_l = readl(&timer->timer_curr_value0);
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| 	timebase_h = readl(&timer->timer_curr_value1);
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| 
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| 	cntr = timebase_h << 32 | timebase_l;
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| 	return cntr;
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| }
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| 
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| #if CONFIG_IS_ENABLED(BOOTSTAGE)
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| ulong timer_get_boot_us(void)
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| {
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| 	uint64_t  ticks = 0;
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| 	uint32_t  rate;
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| 	uint64_t  us;
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| 	int ret;
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| 
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| 	ret = dm_timer_init();
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| 
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| 	if (!ret) {
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| 		/* The timer is available */
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| 		rate = timer_get_rate(gd->timer);
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| 		timer_get_count(gd->timer, &ticks);
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| #if !CONFIG_IS_ENABLED(OF_PLATDATA)
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| 	} else if (ret == -EAGAIN) {
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| 		/* We have been called so early that the DM is not ready,... */
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| 		ofnode node = offset_to_ofnode(-1);
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| 		struct rk_timer *timer = NULL;
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| 
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| 		/*
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| 		 * ... so we try to access the raw timer, if it is specified
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| 		 * via the tick-timer property in /chosen.
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| 		 */
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| 		node = ofnode_get_chosen_node("tick-timer");
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| 		if (!ofnode_valid(node)) {
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| 			debug("%s: no /chosen/tick-timer\n", __func__);
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| 			return 0;
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| 		}
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| 
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| 		timer = (struct rk_timer *)ofnode_get_addr(node);
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| 
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| 		/* This timer is down-counting */
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| 		ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
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| 		if (ofnode_read_u32(node, "clock-frequency", &rate)) {
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| 			debug("%s: could not read clock-frequency\n", __func__);
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| 			return 0;
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| 		}
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| #endif
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| 	} else {
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| 		return 0;
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| 	}
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| 
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| 	us = (ticks * 1000) / rate;
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| 	return us;
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| }
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| #endif
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| 
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| static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
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| {
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| 	struct rockchip_timer_priv *priv = dev_get_priv(dev);
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| 	uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
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| 
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| 	/* timers are down-counting */
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| 	*count = ~0ull - cntr;
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| 	return 0;
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| }
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| 
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| static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
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| {
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| #if !CONFIG_IS_ENABLED(OF_PLATDATA)
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| 	struct rockchip_timer_priv *priv = dev_get_priv(dev);
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| 
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| 	priv->timer = dev_read_addr_ptr(dev);
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| 	if (!priv->timer)
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| 		return -ENOENT;
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| #endif
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| 
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| 	return 0;
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| }
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| 
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| static int rockchip_timer_start(struct udevice *dev)
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| {
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| 	struct rockchip_timer_priv *priv = dev_get_priv(dev);
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| 	const uint64_t reload_val = ~0uLL;
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| 	const uint32_t reload_val_l = reload_val & 0xffffffff;
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| 	const uint32_t reload_val_h = reload_val >> 32;
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| 
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| 	/* don't reinit, if the timer is already running and set up */
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| 	if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
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| 	    (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
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| 	    (readl(&priv->timer->timer_load_count1) == reload_val_h))
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| 		return 0;
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| 
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| 	/* disable timer and reset all control */
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| 	writel(0, &priv->timer->timer_ctrl_reg);
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| 	/* write reload value */
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| 	writel(reload_val_l, &priv->timer->timer_load_count0);
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| 	writel(reload_val_h, &priv->timer->timer_load_count1);
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| 	/* enable timer */
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| 	writel(1, &priv->timer->timer_ctrl_reg);
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| 
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| 	return 0;
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| }
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| 
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| static int rockchip_timer_probe(struct udevice *dev)
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| {
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| #if CONFIG_IS_ENABLED(OF_PLATDATA)
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| 	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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| 	struct rockchip_timer_priv *priv = dev_get_priv(dev);
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| 	struct rockchip_timer_plat *plat = dev_get_platdata(dev);
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| 
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| 	priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
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| 	uc_priv->clock_rate = plat->dtd.clock_frequency;
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| #endif
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| 
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| 	return rockchip_timer_start(dev);
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| }
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| 
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| static const struct timer_ops rockchip_timer_ops = {
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| 	.get_count = rockchip_timer_get_count,
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| };
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| 
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| static const struct udevice_id rockchip_timer_ids[] = {
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| 	{ .compatible = "rockchip,rk3188-timer" },
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| 	{ .compatible = "rockchip,rk3288-timer" },
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| 	{ .compatible = "rockchip,rk3368-timer" },
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| 	{}
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| };
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| 
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| U_BOOT_DRIVER(rockchip_rk3368_timer) = {
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| 	.name	= "rockchip_rk3368_timer",
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| 	.id	= UCLASS_TIMER,
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| 	.of_match = rockchip_timer_ids,
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| 	.probe = rockchip_timer_probe,
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| 	.ops	= &rockchip_timer_ops,
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| 	.priv_auto_alloc_size = sizeof(struct rockchip_timer_priv),
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| #if CONFIG_IS_ENABLED(OF_PLATDATA)
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| 	.platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat),
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| #endif
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| 	.ofdata_to_platdata = rockchip_clk_ofdata_to_platdata,
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| };
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