27 lines
1.5 KiB
Plaintext
27 lines
1.5 KiB
Plaintext
Spin table in cache
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As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
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DDR is initialized and U-Boot relocates itself into DDR, the spin table is
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accessible for core 0. It is part of release.S, within 4KB range after
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__secondary_start_page. For other cores to use the spin table, the booting
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process is described below:
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Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
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is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
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the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot
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page translation for secondary cores to use this page of memory. Then 4KB
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memory is copied from __secondary_start_page to the boot page, after flusing
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cache because this page is mapped as normal DDR. Before copying the reset page,
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core 0 puts the physical address of the spin table (which is in release.S and
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relocated to the top of mapped memory) into a variable __spin_table_addr so
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that secondary cores can see it.
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When secondary cores boot up from 0xffff_f000 page, they only have one default
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TLB. While booting, they set up another TLB in AS=1 space and jump into
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the new space. The new TLB covers the physical address of the spin table page,
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with WIMGE =0b00100. Now secondary cores can keep polling the spin table
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without stress DDR bus because both the code and the spin table is in cache.
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For the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep
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cache coherence.
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