150 lines
3.6 KiB
C
150 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008 by NXP Semiconductors
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* @Author: Kevin Wells
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* @Descr: LPC3250 DMA controller interface support functions
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*
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* Copyright (c) 2015 Tyco Fire Protection Products.
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*/
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#include <common.h>
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#include <errno.h>
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#include <init.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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/* DMA controller channel register structure */
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struct dmac_chan_reg {
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u32 src_addr;
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u32 dest_addr;
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u32 lli;
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u32 control;
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u32 config_ch;
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u32 reserved[3];
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};
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/* DMA controller register structures */
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struct dma_reg {
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u32 int_stat;
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u32 int_tc_stat;
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u32 int_tc_clear;
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u32 int_err_stat;
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u32 int_err_clear;
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u32 raw_tc_stat;
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u32 raw_err_stat;
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u32 chan_enable;
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u32 sw_burst_req;
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u32 sw_single_req;
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u32 sw_last_burst_req;
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u32 sw_last_single_req;
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u32 config;
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u32 sync;
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u32 reserved[50];
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struct dmac_chan_reg dma_chan[8];
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};
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#define DMA_NO_OF_CHANNELS 8
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/* config register definitions */
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#define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
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static u32 alloc_ch;
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static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
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int lpc32xx_dma_get_channel(void)
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{
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int i;
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if (!alloc_ch) { /* First time caller */
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/*
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* DMA clock are enable by "lpc32xx_dma_init()" and should
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* be call by board "board_early_init_f()" function.
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*/
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/*
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* Make sure DMA controller and all channels are disabled.
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* Controller is in little-endian mode. Disable sync signals.
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*/
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writel(0, &dma->config);
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writel(0, &dma->sync);
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/* Clear interrupt and error statuses */
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writel(0xFF, &dma->int_tc_clear);
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writel(0xFF, &dma->raw_tc_stat);
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writel(0xFF, &dma->int_err_clear);
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writel(0xFF, &dma->raw_err_stat);
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/* Enable DMA controller */
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writel(DMAC_CTRL_ENABLE, &dma->config);
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}
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i = ffz(alloc_ch);
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/* Check if all the available channels are busy */
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if (unlikely(i == DMA_NO_OF_CHANNELS))
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return -1;
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alloc_ch |= BIT_MASK(i);
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return i;
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}
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int lpc32xx_dma_start_xfer(unsigned int channel,
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const struct lpc32xx_dmac_ll *desc, u32 config)
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{
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if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) ||
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(channel >= DMA_NO_OF_CHANNELS))) {
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pr_err("Request for xfer on unallocated channel %d", channel);
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return -1;
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}
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writel(BIT_MASK(channel), &dma->int_tc_clear);
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writel(BIT_MASK(channel), &dma->int_err_clear);
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writel(desc->dma_src, &dma->dma_chan[channel].src_addr);
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writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);
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writel(desc->next_lli, &dma->dma_chan[channel].lli);
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writel(desc->next_ctrl, &dma->dma_chan[channel].control);
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writel(config, &dma->dma_chan[channel].config_ch);
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return 0;
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}
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int lpc32xx_dma_wait_status(unsigned int channel)
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{
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unsigned long start;
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u32 reg;
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/* Check if given channel is valid */
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if (unlikely(channel >= DMA_NO_OF_CHANNELS)) {
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pr_err("Request for status on unallocated channel %d", channel);
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return -1;
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}
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start = get_timer(0);
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while (1) {
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reg = readl(&dma->raw_tc_stat);
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reg |= readl(dma->raw_err_stat);
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if (reg & BIT_MASK(channel))
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break;
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if (get_timer(start) > CONFIG_SYS_HZ) {
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pr_err("DMA status timeout channel %d\n", channel);
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {
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setbits_le32(&dma->int_err_clear, BIT_MASK(channel));
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setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));
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pr_err("DMA error on channel %d\n", channel);
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return -1;
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}
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setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));
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setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));
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return 0;
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}
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