628 lines
14 KiB
C
628 lines
14 KiB
C
#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/nx_gpio.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2CSTAT_MTM 0xC0 /* Master Transmit Mode */
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#define I2CSTAT_MRM 0x80 /* Master Receive Mode */
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#define I2CSTAT_BSY 0x20 /* Read: Bus Busy */
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#define I2CSTAT_SS 0x20 /* Write: START (1) / STOP (0) */
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#define I2CSTAT_RXTXEN 0x10 /* Rx/Tx enable */
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#define I2CSTAT_ABT 0x08 /* Arbitration bit */
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#define I2CSTAT_NACK 0x01 /* Nack bit */
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#define I2CCON_IRCLR 0x100 /* Interrupt Clear bit */
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#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
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#define I2CCON_TCP256 0x40 /* Tx-clock prescaler: 16 (0) / 256 (1) */
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#define I2CCON_IRENB 0x20 /* Interrupt Enable bit */
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#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
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#define I2CCON_TCDMSK 0x0F /* I2C-bus transmit clock divider bit mask */
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#ifdef CONFIG_ARCH_S5P6818
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#define SDADLY_CLKSTEP 5 /* SDA delay: Reg. val. is multiple of 5 clks */
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#define SDADLY_MAX 3 /* SDA delay: Max. reg. value is 3 */
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#define I2CLC_FILTER 0x04 /* SDA filter on */
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#else
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#define STOPCON_CLR 0x01 /* Clock Line Release */
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#define STOPCON_DLR 0x02 /* Data Line Release */
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#define STOPCON_NAG 0x04 /* not-ackn. generation and data shift cont. */
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#endif
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#define I2C_TIMEOUT_MS 10 /* 10 ms */
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#define I2C_M_NOSTOP 0x100
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#define MAX_I2C_NUM 3
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#define DEFAULT_SPEED 100000 /* default I2C speed [Hz] */
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DECLARE_GLOBAL_DATA_PTR;
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struct nx_i2c_regs {
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uint iiccon;
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uint iicstat;
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uint iicadd;
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uint iicds;
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#ifdef CONFIG_ARCH_S5P6818
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/* S5P6818: Offset 0x10 is Line Control Register (SDA-delay, Filter) */
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uint iiclc;
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#else
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/* S5P4418: Offset 0x10 is Stop Control Register */
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uint iicstopcon;
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#endif
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};
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struct nx_i2c_bus {
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uint bus_num;
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struct nx_i2c_regs *regs;
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uint speed;
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uint target_speed;
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#ifdef CONFIG_ARCH_S5P6818
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uint sda_delay;
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#else
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/* setup time for Stop condition [us] */
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uint tsu_stop;
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#endif
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};
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/* s5pxx18 i2c must be reset before enabled */
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static void i2c_reset(int ch)
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{
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int rst_id = RESET_ID_I2C0 + ch;
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nx_rstcon_setrst(rst_id, 0);
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nx_rstcon_setrst(rst_id, 1);
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}
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static uint i2c_get_clkrate(struct nx_i2c_bus *bus)
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{
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struct clk *clk;
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int index = bus->bus_num;
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char name[50] = {0, };
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sprintf(name, "%s.%d", DEV_NAME_I2C, index);
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clk = clk_get((const char *)name);
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if (!clk)
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return -1;
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return clk_get_rate(clk);
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}
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static uint i2c_set_clk(struct nx_i2c_bus *bus, uint enb)
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{
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struct clk *clk;
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char name[50];
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sprintf(name, "%s.%d", DEV_NAME_I2C, bus->bus_num);
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clk = clk_get((const char *)name);
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if (!clk) {
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debug("%s(): clk_get(%s) error!\n",
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__func__, (const char *)name);
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return -EINVAL;
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}
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clk_disable(clk);
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if (enb)
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clk_enable(clk);
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return 0;
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}
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#ifdef CONFIG_ARCH_S5P6818
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/* Set SDA line delay, not available at S5P4418 */
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static int nx_i2c_set_sda_delay(struct nx_i2c_bus *bus)
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{
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struct nx_i2c_regs *i2c = bus->regs;
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uint pclk = 0;
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uint t_pclk = 0;
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uint delay = 0;
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/* get input clock of the I2C-controller */
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pclk = i2c_get_clkrate(bus);
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if (bus->sda_delay) {
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/* t_pclk = period time of one pclk [ns] */
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t_pclk = DIV_ROUND_UP(1000, pclk / 1000000);
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/* delay = number of pclks required for sda_delay [ns] */
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delay = DIV_ROUND_UP(bus->sda_delay, t_pclk);
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/* delay = register value (step of 5 clocks) */
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delay = DIV_ROUND_UP(delay, SDADLY_CLKSTEP);
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/* max. possible register value = 3 */
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if (delay > SDADLY_MAX) {
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delay = SDADLY_MAX;
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debug("%s(): sda-delay des.: %dns, sat. to max.: %dns (granularity: %dns)\n",
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__func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
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t_pclk * SDADLY_CLKSTEP);
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} else {
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debug("%s(): sda-delay des.: %dns, act.: %dns (granularity: %dns)\n",
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__func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
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t_pclk * SDADLY_CLKSTEP);
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}
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delay |= I2CLC_FILTER;
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} else {
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delay = 0;
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debug("%s(): sda-delay = 0\n", __func__);
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}
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delay &= 0x7;
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writel(delay, &i2c->iiclc);
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return 0;
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}
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#endif
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static int nx_i2c_set_bus_speed(struct udevice *dev, uint speed)
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{
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struct nx_i2c_bus *bus = dev_get_priv(dev);
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struct nx_i2c_regs *i2c = bus->regs;
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unsigned long pclk, pres = 16, div;
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if (i2c_set_clk(bus, 1))
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return -EINVAL;
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/* get input clock of the I2C-controller */
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pclk = i2c_get_clkrate(bus);
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/* calculate prescaler and divisor values */
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if ((pclk / pres / (16 + 1)) > speed)
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/* prescaler value 16 is too less --> set to 256 */
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pres = 256;
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div = 0;
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/* actual divider = div + 1 */
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while ((pclk / pres / (div + 1)) > speed)
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div++;
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if (div > 0xF) {
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debug("%s(): pres==%ld, div==0x%lx is saturated to 0xF !)\n",
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__func__, pres, div);
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div = 0xF;
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} else {
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debug("%s(): pres==%ld, div==0x%lx)\n", __func__, pres, div);
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}
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/* set Tx-clock divisor and prescaler values */
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writel((div & I2CCON_TCDMSK) | ((pres == 256) ? I2CCON_TCP256 : 0),
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&i2c->iiccon);
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/* init to SLAVE REVEIVE and set slaveaddr */
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writel(0, &i2c->iicstat);
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writel(0x00, &i2c->iicadd);
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/* program Master Transmit (and implicit STOP) */
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writel(I2CSTAT_MTM | I2CSTAT_RXTXEN, &i2c->iicstat);
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/* calculate actual I2C speed [Hz] */
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bus->speed = pclk / ((div + 1) * pres);
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debug("%s(): speed des.: %dHz, act.: %dHz\n",
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__func__, speed, bus->speed);
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#ifdef CONFIG_ARCH_S5P6818
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nx_i2c_set_sda_delay(bus);
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#else
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/* setup time for Stop condition [us], min. 4us @ 100kHz I2C-clock */
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bus->tsu_stop = DIV_ROUND_UP(400, bus->speed / 1000);
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#endif
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if (i2c_set_clk(bus, 0))
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return -EINVAL;
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return 0;
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}
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static void i2c_process_node(struct udevice *dev)
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{
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struct nx_i2c_bus *bus = dev_get_priv(dev);
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bus->target_speed = dev_read_s32_default(dev, "clock-frequency",
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DEFAULT_SPEED);
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#ifdef CONFIG_ARCH_S5P6818
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bus->sda_delay = dev_read_s32_default(dev, "i2c-sda-delay-ns", 0);
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#endif
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}
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static int nx_i2c_probe(struct udevice *dev)
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{
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struct nx_i2c_bus *bus = dev_get_priv(dev);
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fdt_addr_t addr;
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/* get regs = i2c base address */
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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bus->regs = (struct nx_i2c_regs *)addr;
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bus->bus_num = dev_seq(dev);
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/* i2c node parsing */
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i2c_process_node(dev);
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if (!bus->target_speed)
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return -ENODEV;
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/* reset */
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i2c_reset(bus->bus_num);
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return 0;
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}
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/* i2c bus busy check */
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static int i2c_is_busy(struct nx_i2c_regs *i2c)
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{
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ulong start_time;
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start_time = get_timer(0);
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while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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if (get_timer(start_time) > I2C_TIMEOUT_MS) {
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debug("Timeout\n");
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return -EBUSY;
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}
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}
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return 0;
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}
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/* irq enable/disable functions */
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static void i2c_enable_irq(struct nx_i2c_regs *i2c)
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{
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unsigned int reg;
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reg = readl(&i2c->iiccon);
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reg |= I2CCON_IRENB;
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writel(reg, &i2c->iiccon);
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}
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/* irq clear function */
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static void i2c_clear_irq(struct nx_i2c_regs *i2c)
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{
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unsigned int reg;
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reg = readl(&i2c->iiccon);
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/* reset interrupt pending flag */
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reg &= ~(I2CCON_IRPND);
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/*
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* Interrupt must also be cleared!
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* Otherwise linux boot may hang after:
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* [ 0.436000] NetLabel: unlabeled traffic allowed by default
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* Next would be:
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* [ 0.442000] clocksource: Switched to clocksource source timer
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*/
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reg |= I2CCON_IRCLR;
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writel(reg, &i2c->iiccon);
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}
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/* ack enable functions */
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static void i2c_enable_ack(struct nx_i2c_regs *i2c)
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{
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unsigned int reg;
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reg = readl(&i2c->iiccon);
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reg |= I2CCON_ACKGEN;
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writel(reg, &i2c->iiccon);
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}
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static void i2c_send_stop(struct nx_i2c_bus *bus)
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{
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struct nx_i2c_regs *i2c = bus->regs;
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if (IS_ENABLED(CONFIG_ARCH_S5P6818)) {
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unsigned int reg;
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reg = readl(&i2c->iicstat);
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reg |= I2CSTAT_MRM | I2CSTAT_RXTXEN;
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reg &= (~I2CSTAT_SS);
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writel(reg, &i2c->iicstat);
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i2c_clear_irq(i2c);
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} else { /* S5P4418 */
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writel(STOPCON_NAG, &i2c->iicstopcon);
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i2c_clear_irq(i2c);
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/*
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* Clock Line Release --> SDC changes from Low to High and
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* SDA from High to Low
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*/
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writel(STOPCON_CLR, &i2c->iicstopcon);
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/* Hold SDA Low (Setup Time for Stop condition) */
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udelay(bus->tsu_stop);
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i2c_clear_irq(i2c);
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/* Master Receive Mode Stop --> SDA becomes High */
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writel(I2CSTAT_MRM, &i2c->iicstat);
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}
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}
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static int wait_for_xfer(struct nx_i2c_regs *i2c)
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{
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unsigned long start_time = get_timer(0);
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do {
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if (readl(&i2c->iiccon) & I2CCON_IRPND)
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/* return -EREMOTEIO if not Acknowledged, otherwise 0 */
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return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
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-EREMOTEIO : 0;
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} while (get_timer(start_time) < I2C_TIMEOUT_MS);
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return -ETIMEDOUT;
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}
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static int i2c_transfer(struct nx_i2c_regs *i2c,
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uchar cmd_type,
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uchar chip_addr,
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uchar addr[],
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uchar addr_len,
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uchar data[],
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unsigned short data_len,
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uint seq)
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{
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uint status;
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int i = 0, result;
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/* Note: data_len = 0 is supported for "probe_chip" */
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i2c_enable_irq(i2c);
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i2c_enable_ack(i2c);
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/* Get the slave chip address going */
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/* Enable Rx/Tx */
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writel(I2CSTAT_RXTXEN, &i2c->iicstat);
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writel(chip_addr, &i2c->iicds);
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status = I2CSTAT_RXTXEN | I2CSTAT_SS;
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if (cmd_type == I2C_WRITE || (addr && addr_len))
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status |= I2CSTAT_MTM;
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else
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status |= I2CSTAT_MRM;
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writel(status, &i2c->iicstat);
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if (seq)
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i2c_clear_irq(i2c);
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/* Wait for chip address to transmit. */
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result = wait_for_xfer(i2c);
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if (result) {
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debug("%s: transmitting chip address failed\n", __func__);
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goto bailout;
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}
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/* If register address needs to be transmitted - do it now. */
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if (addr && addr_len) { /* register addr */
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while ((i < addr_len) && !result) {
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writel(addr[i++], &i2c->iicds);
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i2c_clear_irq(i2c);
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result = wait_for_xfer(i2c);
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}
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i = 0;
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if (result) {
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debug("%s: transmitting register address failed\n",
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__func__);
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goto bailout;
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}
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}
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switch (cmd_type) {
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case I2C_WRITE:
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while ((i < data_len) && !result) {
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writel(data[i++], &i2c->iicds);
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i2c_clear_irq(i2c);
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result = wait_for_xfer(i2c);
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}
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break;
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case I2C_READ:
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if (addr && addr_len) {
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/*
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* Register address has been sent, now send slave chip
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* address again to start the actual read transaction.
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*/
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writel(chip_addr, &i2c->iicds);
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/* Generate a re-START. */
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writel(I2CSTAT_MRM | I2CSTAT_RXTXEN |
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I2CSTAT_SS, &i2c->iicstat);
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i2c_clear_irq(i2c);
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result = wait_for_xfer(i2c);
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if (result) {
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debug("%s: I2C_READ: sending chip addr. failed\n",
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__func__);
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goto bailout;
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}
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}
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while ((i < data_len) && !result) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
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i2c_clear_irq(i2c);
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result = wait_for_xfer(i2c);
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data[i++] = readb(&i2c->iicds);
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}
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if (result == -EREMOTEIO)
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/* Not Acknowledged --> normal terminated read. */
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result = 0;
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else if (result == -ETIMEDOUT)
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debug("%s: I2C_READ: time out\n", __func__);
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else
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debug("%s: I2C_READ: read not terminated with NACK\n",
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__func__);
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break;
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default:
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debug("%s: bad call\n", __func__);
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result = -EINVAL;
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break;
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}
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bailout:
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return result;
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}
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static int nx_i2c_read(struct udevice *dev, uchar chip_addr, uint addr,
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uint alen, uchar *buffer, uint len, uint seq)
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{
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struct nx_i2c_bus *i2c;
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uchar xaddr[4];
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int ret;
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i2c = dev_get_priv(dev);
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if (!i2c)
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return -EFAULT;
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if (alen > 4) {
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debug("I2C read: addr len %d not supported\n", alen);
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return -EADDRNOTAVAIL;
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}
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if (alen > 0)
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xaddr[0] = (addr >> 24) & 0xFF;
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if (alen > 0) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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}
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ret = i2c_transfer(i2c->regs, I2C_READ, chip_addr << 1,
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&xaddr[4 - alen], alen, buffer, len, seq);
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if (ret) {
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debug("I2C read failed %d\n", ret);
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return -EIO;
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}
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return 0;
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}
|
|
|
|
static int nx_i2c_write(struct udevice *dev, uchar chip_addr, uint addr,
|
|
uint alen, uchar *buffer, uint len, uint seq)
|
|
{
|
|
struct nx_i2c_bus *i2c;
|
|
uchar xaddr[4];
|
|
int ret;
|
|
|
|
i2c = dev_get_priv(dev);
|
|
if (!i2c)
|
|
return -EFAULT;
|
|
|
|
if (alen > 4) {
|
|
debug("I2C write: addr len %d not supported\n", alen);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (alen > 0) {
|
|
xaddr[0] = (addr >> 24) & 0xFF;
|
|
xaddr[1] = (addr >> 16) & 0xFF;
|
|
xaddr[2] = (addr >> 8) & 0xFF;
|
|
xaddr[3] = addr & 0xFF;
|
|
}
|
|
|
|
ret = i2c_transfer(i2c->regs, I2C_WRITE, chip_addr << 1,
|
|
&xaddr[4 - alen], alen, buffer, len, seq);
|
|
if (ret) {
|
|
debug("I2C write failed %d\n", ret);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nx_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
|
|
{
|
|
struct nx_i2c_bus *bus = dev_get_priv(dev);
|
|
struct nx_i2c_regs *i2c = bus->regs;
|
|
int ret;
|
|
int i;
|
|
|
|
/* The power loss by the clock, only during on/off. */
|
|
ret = i2c_set_clk(bus, 1);
|
|
|
|
if (!ret)
|
|
/* Bus State(Busy) check */
|
|
ret = i2c_is_busy(i2c);
|
|
if (!ret) {
|
|
for (i = 0; i < nmsgs; msg++, i++) {
|
|
if (msg->flags & I2C_M_RD) {
|
|
ret = nx_i2c_read(dev, msg->addr, 0, 0,
|
|
msg->buf, msg->len, i);
|
|
} else {
|
|
ret = nx_i2c_write(dev, msg->addr, 0, 0,
|
|
msg->buf, msg->len, i);
|
|
}
|
|
|
|
if (ret) {
|
|
debug("i2c_xfer: error sending\n");
|
|
ret = -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
i2c_send_stop(bus);
|
|
if (i2c_set_clk(bus, 0))
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
};
|
|
|
|
static int nx_i2c_probe_chip(struct udevice *dev, u32 chip_addr,
|
|
u32 chip_flags)
|
|
{
|
|
int ret;
|
|
struct nx_i2c_bus *bus = dev_get_priv(dev);
|
|
|
|
ret = i2c_set_clk(bus, 1);
|
|
|
|
if (!ret) {
|
|
/*
|
|
* Send Chip Address only
|
|
* --> I2C transfer with data length and address length = 0.
|
|
* If there is a Slave, i2c_transfer() returns 0 (acknowledge
|
|
* transfer).
|
|
* I2C_WRITE must be used in order Master Transmit Mode is
|
|
* selected. Otherwise (in Master Receive Mode, I2C_READ)
|
|
* sending the stop condition below is not working (SDA does
|
|
* not transit to High).
|
|
*/
|
|
ret = i2c_transfer(bus->regs, I2C_WRITE, (uchar)chip_addr << 1,
|
|
NULL, 0, NULL, 0, 0);
|
|
|
|
i2c_send_stop(bus);
|
|
if (i2c_set_clk(bus, 0))
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dm_i2c_ops nx_i2c_ops = {
|
|
.xfer = nx_i2c_xfer,
|
|
.probe_chip = nx_i2c_probe_chip,
|
|
.set_bus_speed = nx_i2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct udevice_id nx_i2c_ids[] = {
|
|
{ .compatible = "nexell,s5pxx18-i2c" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_nexell) = {
|
|
.name = "i2c_nexell",
|
|
.id = UCLASS_I2C,
|
|
.of_match = nx_i2c_ids,
|
|
.probe = nx_i2c_probe,
|
|
.priv_auto = sizeof(struct nx_i2c_bus),
|
|
.ops = &nx_i2c_ops,
|
|
};
|