371 lines
8.7 KiB
C
371 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* max98090.c -- MAX98090 ALSA SoC Audio driver
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*
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* Copyright 2011 Maxim Integrated Products
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*/
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#include <common.h>
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#include <audio_codec.h>
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#include <div64.h>
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#include <dm.h>
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#include <i2c.h>
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#include <i2s.h>
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#include <sound.h>
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#include <asm/gpio.h>
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#include "maxim_codec.h"
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#include "max98090.h"
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/*
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* Sets hw params for max98090
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*
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* @priv: max98090 information pointer
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* @rate: Sampling rate
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* @bits_per_sample: Bits per sample
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*
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* @return -EIO for error, 0 for success.
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*/
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int max98090_hw_params(struct maxim_priv *priv, unsigned int rate,
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unsigned int bits_per_sample)
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{
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int error;
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unsigned char value;
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switch (bits_per_sample) {
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case 16:
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maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
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error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT,
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M98090_WS_MASK, 0);
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maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
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break;
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default:
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debug("%s: Illegal bits per sample %d.\n",
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__func__, bits_per_sample);
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return -1;
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}
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/* Update filter mode */
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if (rate < 240000)
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error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
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M98090_MODE_MASK, 0);
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else
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error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
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M98090_MODE_MASK, M98090_MODE_MASK);
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/* Update sample rate mode */
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if (rate < 50000)
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error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
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M98090_DHF_MASK, 0);
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else
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error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
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M98090_DHF_MASK, M98090_DHF_MASK);
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if (error < 0) {
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debug("%s: Error setting hardware params.\n", __func__);
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return -EIO;
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}
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priv->rate = rate;
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return 0;
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}
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/*
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* Configures Audio interface system clock for the given frequency
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*
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* @priv: max98090 information
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* @freq: Sampling frequency in Hz
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*
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* @return -EIO for error, 0 for success.
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*/
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int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq)
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{
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int error = 0;
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/* Requested clock frequency is already setup */
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if (freq == priv->sysclk)
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return 0;
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/* Setup clocks for slave mode, and using the PLL
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* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
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* 0x02 (when master clk is 20MHz to 40MHz)..
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* 0x03 (when master clk is 40MHz to 60MHz)..
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*/
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if (freq >= 10000000 && freq < 20000000) {
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error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV1);
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} else if (freq >= 20000000 && freq < 40000000) {
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error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV2);
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} else if (freq >= 40000000 && freq < 60000000) {
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error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV4);
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} else {
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debug("%s: Invalid master clock frequency\n", __func__);
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return -1;
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}
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debug("%s: Clock at %uHz\n", __func__, freq);
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if (error < 0)
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return -1;
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priv->sysclk = freq;
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return 0;
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}
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/*
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* Sets Max98090 I2S format
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*
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* @priv: max98090 information
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* @fmt: i2S format - supports a subset of the options defined in i2s.h.
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*
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* @return -EIO for error, 0 for success.
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*/
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int max98090_set_fmt(struct maxim_priv *priv, int fmt)
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{
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u8 regval = 0;
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int error = 0;
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if (fmt == priv->fmt)
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return 0;
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priv->fmt = fmt;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* Set to slave mode PLL - MAS mode off */
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error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB,
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0x00);
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error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB,
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0x00);
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error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE,
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M98090_USE_M1_MASK, 0);
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* Set to master mode */
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debug("Master mode not supported\n");
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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case SND_SOC_DAIFMT_CBM_CFS:
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default:
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debug("%s: Clock mode unsupported\n", __func__);
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return -EINVAL;
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}
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error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval);
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regval = 0;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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regval |= M98090_DLY_MASK;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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regval |= M98090_RJ_MASK;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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/* Not supported mode */
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default:
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debug("%s: Unrecognized format.\n", __func__);
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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regval |= M98090_WCI_MASK;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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regval |= M98090_BCI_MASK;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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regval |= M98090_BCI_MASK | M98090_WCI_MASK;
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break;
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default:
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debug("%s: Unrecognized inversion settings.\n", __func__);
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return -EINVAL;
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}
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error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval);
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if (error < 0) {
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debug("%s: Error setting i2s format.\n", __func__);
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return -EIO;
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}
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return 0;
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}
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/*
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* resets the audio codec
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*
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* @priv: max98090 information
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* @return -EIO for error, 0 for success.
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*/
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static int max98090_reset(struct maxim_priv *priv)
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{
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int ret;
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/*
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* Gracefully reset the DSP core and the codec hardware in a proper
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* sequence.
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*/
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ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET,
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M98090_SWRESET_MASK);
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if (ret != 0) {
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debug("%s: Failed to reset DSP: %d\n", __func__, ret);
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return ret;
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}
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mdelay(20);
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return 0;
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}
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/*
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* Initialise max98090 codec device
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*
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* @priv: max98090 information
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*
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* @return -EIO for error, 0 for success.
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*/
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int max98090_device_init(struct maxim_priv *priv)
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{
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unsigned char id;
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int error = 0;
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/* reset the codec, the DSP core, and disable all interrupts */
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error = max98090_reset(priv);
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if (error != 0) {
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debug("Reset\n");
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return error;
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}
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/* initialize private data */
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priv->sysclk = -1U;
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priv->rate = -1U;
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priv->fmt = -1U;
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error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id);
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if (error < 0) {
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debug("%s: Failure reading hardware revision: %d\n",
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__func__, id);
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return -EIO;
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}
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debug("%s: Hardware revision: %d\n", __func__, id);
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return 0;
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}
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static int max98090_setup_interface(struct maxim_priv *priv)
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{
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unsigned char id;
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int error;
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/* Reading interrupt status to clear them */
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error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id);
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error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL,
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M98090_DACHP_MASK);
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error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL,
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M98090_VCM_MODE_MASK);
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error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1);
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error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2);
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error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25);
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error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
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error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
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error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
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error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0);
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error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0);
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error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
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M98090_SDIEN_MASK);
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error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN,
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M98090_SHDNN_MASK);
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error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE,
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M98090_HPREN_MASK | M98090_HPLEN_MASK |
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M98090_SPREN_MASK | M98090_SPLEN_MASK |
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M98090_DAREN_MASK | M98090_DALEN_MASK);
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error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
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M98090_SDOEN_MASK | M98090_SDIEN_MASK);
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if (error < 0)
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return -EIO;
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return 0;
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}
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static int max98090_do_init(struct maxim_priv *priv, int sampling_rate,
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int mclk_freq, int bits_per_sample)
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{
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int ret = 0;
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ret = max98090_setup_interface(priv);
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if (ret < 0) {
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debug("%s: max98090 setup interface failed\n", __func__);
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return ret;
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}
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ret = max98090_set_sysclk(priv, mclk_freq);
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if (ret < 0) {
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debug("%s: max98090 codec set sys clock failed\n", __func__);
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return ret;
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}
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ret = max98090_hw_params(priv, sampling_rate, bits_per_sample);
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if (ret == 0) {
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ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S |
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SND_SOC_DAIFMT_NB_NF |
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SND_SOC_DAIFMT_CBS_CFS);
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}
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return ret;
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}
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static int max98090_set_params(struct udevice *dev, int interface, int rate,
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int mclk_freq, int bits_per_sample,
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uint channels)
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{
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struct maxim_priv *priv = dev_get_priv(dev);
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return max98090_do_init(priv, rate, mclk_freq, bits_per_sample);
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}
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static int max98090_probe(struct udevice *dev)
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{
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struct maxim_priv *priv = dev_get_priv(dev);
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int ret;
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priv->dev = dev;
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ret = max98090_device_init(priv);
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if (ret < 0) {
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debug("%s: max98090 codec chip init failed\n", __func__);
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return ret;
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}
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return 0;
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}
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static const struct audio_codec_ops max98090_ops = {
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.set_params = max98090_set_params,
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};
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static const struct udevice_id max98090_ids[] = {
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{ .compatible = "maxim,max98090" },
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{ }
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};
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U_BOOT_DRIVER(max98090) = {
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.name = "max98090",
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.id = UCLASS_AUDIO_CODEC,
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.of_match = max98090_ids,
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.probe = max98090_probe,
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.ops = &max98090_ops,
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.priv_auto_alloc_size = sizeof(struct maxim_priv),
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};
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