8f2e2f15ff
According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> |
||
|---|---|---|
| .. | ||
| Kconfig | ||
| Makefile | ||
| clock.c | ||
| ddr.c | ||
| mp.c | ||
| soc.c | ||