121 lines
2.5 KiB
C
121 lines
2.5 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/arch/flow.h>
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#include <asm/arch/powergate.h>
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#include <asm/arch/tegra.h>
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#define PWRGATE_TOGGLE 0x30
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#define PWRGATE_TOGGLE_START (1 << 8)
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#define REMOVE_CLAMPING 0x34
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#define PWRGATE_STATUS 0x38
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static int tegra_powergate_set(enum tegra_powergate id, bool state)
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{
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u32 value, mask = state ? (1 << id) : 0, old_mask;
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unsigned long start, timeout = 25;
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value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
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old_mask = value & (1 << id);
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if (mask == old_mask)
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return 0;
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writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
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if ((value & (1 << id)) == mask)
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return 0;
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}
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return -ETIMEDOUT;
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}
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int tegra_powergate_power_on(enum tegra_powergate id)
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{
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return tegra_powergate_set(id, true);
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}
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int tegra_powergate_power_off(enum tegra_powergate id)
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{
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return tegra_powergate_set(id, false);
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}
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static int tegra_powergate_remove_clamping(enum tegra_powergate id)
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{
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unsigned long value;
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/*
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* The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
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* partitions reversed. This was originally introduced on Tegra20 but
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* has since been carried forward for backwards-compatibility.
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*/
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if (id == TEGRA_POWERGATE_VDEC)
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value = 1 << TEGRA_POWERGATE_PCIE;
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else if (id == TEGRA_POWERGATE_PCIE)
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value = 1 << TEGRA_POWERGATE_VDEC;
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else
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value = 1 << id;
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writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
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return 0;
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}
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static void tegra_powergate_ram_repair(void)
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{
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#ifdef CONFIG_TEGRA124
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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/* Request RAM repair for cluster 0 and wait until complete */
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setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
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while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
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;
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/* Same for cluster 1 */
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setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
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while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
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;
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#endif
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}
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int tegra_powergate_sequence_power_up(enum tegra_powergate id,
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enum periph_id periph)
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{
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int err;
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tegra_powergate_ram_repair();
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reset_set_enable(periph, 1);
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err = tegra_powergate_power_on(id);
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if (err < 0)
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return err;
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clock_enable(periph);
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udelay(10);
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err = tegra_powergate_remove_clamping(id);
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if (err < 0)
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return err;
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udelay(10);
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reset_set_enable(periph, 0);
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return 0;
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}
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